mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 03:49:43 +09:00
12ffe75819
Modify dts files to add 'no-1-8-v' property for all the ZynqMP boards. User can remove this property to enable the UHS mode. This is to keep the same speed (HS) modes across all the stages of the Linux Boot. Due to power cycling limitation of some of the ZynqMP boards, some SD cards don't get power cycled and are failing in Linux. Signed-off-by: Manish Narani <manish.narani@xilinx.com>
597 lines
14 KiB
Plaintext
597 lines
14 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* dts file for Xilinx ZynqMP ZCU216
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*
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* (C) Copyright 2017 - 2020, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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model = "ZynqMP ZCU216 RevA";
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compatible = "xlnx,zynqmp-zcu216-revA", "xlnx,zynqmp-zcu216", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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xlnx,eeprom = <&eeprom>;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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sw19 {
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label = "sw19";
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gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_DOWN>;
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wakeup-source;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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heartbeat_led {
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label = "heartbeat";
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gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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ina226-vccint {
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compatible = "iio-hwmon";
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io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
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};
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ina226-vccint-io-bram-ps {
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compatible = "iio-hwmon";
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io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
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};
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ina226-vcc1v8 {
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compatible = "iio-hwmon";
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io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
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};
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ina226-vcc1v2 {
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compatible = "iio-hwmon";
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io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
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};
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ina226-vadj-fmc {
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compatible = "iio-hwmon";
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io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
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};
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ina226-mgtavcc {
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compatible = "iio-hwmon";
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io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
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};
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ina226-mgt1v2 {
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compatible = "iio-hwmon";
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io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
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};
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ina226-mgt1v8 {
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compatible = "iio-hwmon";
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io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
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};
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ina226-vccint-ams {
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compatible = "iio-hwmon";
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io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
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};
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ina226-dac-avtt {
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compatible = "iio-hwmon";
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io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
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};
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ina226-dac-avccaux {
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compatible = "iio-hwmon";
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io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
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};
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ina226-adc-avcc {
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compatible = "iio-hwmon";
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io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
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};
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ina226-adc-avccaux {
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compatible = "iio-hwmon";
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io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
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};
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ina226-dac-avcc {
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compatible = "iio-hwmon";
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io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
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};
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};
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&dcc {
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status = "okay";
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};
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&fpd_dma_chan1 {
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status = "okay";
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};
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&fpd_dma_chan2 {
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status = "okay";
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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};
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&gem3 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: ethernet-phy@c {
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reg = <0xc>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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ti,dp83867-rxctrl-strap-quirk;
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};
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};
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&gpio {
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status = "okay";
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gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
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"QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
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"QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
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"I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
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"", "", "BUTTON", "LED", "", /* 20 - 24 */
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"", "PMU_INPUT", "", "", "", /* 25 - 29 */
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"", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
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"PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
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"SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
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"SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
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"SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
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"USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
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"USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
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"ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
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"ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
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"ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
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"", "", /* 78 - 79 */
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"", "", "", "", "", /* 80 - 84 */
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"", "", "", "", "", /* 85 -89 */
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"", "", "", "", "", /* 90 - 94 */
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"", "", "", "", "", /* 95 - 99 */
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"", "", "", "", "", /* 100 - 104 */
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"", "", "", "", "", /* 105 - 109 */
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"", "", "", "", "", /* 110 - 114 */
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"", "", "", "", "", /* 115 - 119 */
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"", "", "", "", "", /* 120 - 124 */
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"", "", "", "", "", /* 125 - 129 */
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"", "", "", "", "", /* 130 - 134 */
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"", "", "", "", "", /* 135 - 139 */
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"", "", "", "", "", /* 140 - 144 */
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"", "", "", "", "", /* 145 - 149 */
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"", "", "", "", "", /* 150 - 154 */
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"", "", "", "", "", /* 155 - 159 */
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"", "", "", "", "", /* 160 - 164 */
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"", "", "", "", "", /* 165 - 169 */
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"", "", "", ""; /* 170 - 174 */
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};
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&gpu {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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tca6416_u15: gpio@20 { /* u15 */
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller; /* interrupt not connected */
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#gpio-cells = <2>;
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gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "", /* 0 - 3 */
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"", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
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"FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
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"", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
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};
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i2c-mux@75 { /* u17 */
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* PS_PMBUS */
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/* PMBUS_ALERT done via pca9544 */
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vccint: ina226@40 { /* u65 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vccint";
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reg = <0x40>;
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shunt-resistor = <5000>;
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};
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vccint_io_bram_ps: ina226@41 { /* u57 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vccint-io-bram-ps";
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reg = <0x41>;
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shunt-resistor = <5000>;
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};
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vcc1v8: ina226@42 { /* u60 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc1v8";
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reg = <0x42>;
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shunt-resistor = <2000>;
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};
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vcc1v2: ina226@43 { /* u58 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vcc1v2";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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vadj_fmc: ina226@45 { /* u62 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vadj-fmc";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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mgtavcc: ina226@46 { /* u67 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-mgtavcc";
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reg = <0x46>;
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shunt-resistor = <2000>;
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};
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mgt1v2: ina226@47 { /* u63 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-mgt1v2";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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mgt1v8: ina226@48 { /* u64 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-mgt1v8";
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reg = <0x48>;
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shunt-resistor = <5000>;
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};
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vccint_ams: ina226@49 { /* u61 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-vccint-ams";
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reg = <0x49>;
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shunt-resistor = <5000>;
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};
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dac_avtt: ina226@4a { /* u59 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-dac-avtt";
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reg = <0x4a>;
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shunt-resistor = <5000>;
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};
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dac_avccaux: ina226@4b { /* u124 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-dac-avccaux";
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reg = <0x4b>;
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shunt-resistor = <5000>;
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};
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adc_avcc: ina226@4c { /* u75 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-adc-avcc";
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reg = <0x4c>;
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shunt-resistor = <5000>;
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};
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adc_avccaux: ina226@4d { /* u71 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-adc-avccaux";
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reg = <0x4d>;
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shunt-resistor = <5000>;
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};
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dac_avcc: ina226@4e { /* u77 */
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compatible = "ti,ina226";
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#io-channel-cells = <1>;
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label = "ina226-dac-avcc";
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reg = <0x4e>;
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shunt-resistor = <5000>;
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};
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* NC */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* u104 - ir35215 0x10/0x40 */
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/* u127 - ir38164 0x1b/0x4b */
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/* u112 - ir38164 0x13/0x43 */
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/* u123 - ir38164 0x1c/0x4c */
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irps5401_44: irps54012@44 { /* IRPS5401 - u53 */
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#clock-cells = <0>;
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compatible = "infineon,irps5401";
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reg = <0x44>; /* i2c addr 0x14 */
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};
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irps5401_45: irps54012@45 { /* IRPS5401 - u55 */
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#clock-cells = <0>;
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compatible = "infineon,irps5401";
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reg = <0x45>; /* i2c addr 0x15 */
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};
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/* J21 header too */
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* SYSMON */
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};
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};
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/* u38 MPS430 */
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-mux@74 {
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compatible = "nxp,pca9548"; /* u20 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
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i2c_eeprom: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/*
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* IIC_EEPROM 1kB memory which uses 256B blocks
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* where every block has different address.
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* 0 - 256B address 0x54
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* 256B - 512B address 0x55
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* 512B - 768B address 0x56
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* 768B - 1024B address 0x57
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*/
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eeprom: eeprom@54 { /* u21 */
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compatible = "atmel,24c128";
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reg = <0x54>;
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};
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};
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i2c_si5341: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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si5341: clock-generator@36 { /* SI5341 - u43 */
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compatible = "si5341";
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reg = <0x36>;
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};
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};
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i2c_si570_user_c0: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <300000000>;
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clock-frequency = <300000000>;
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clock-output-names = "si570_user_c0";
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};
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};
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i2c_si570_mgt: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <156250000>;
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clock-frequency = <148500000>;
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clock-output-names = "si570_mgt";
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};
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};
|
|
i2c_8a34001: i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
/* U409B - 8a34001 */
|
|
};
|
|
i2c_clk104: i2c@5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
/* CLK104_SDA */
|
|
};
|
|
i2c@6 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
/* RFMCP connector */
|
|
};
|
|
/* 7 NC */
|
|
};
|
|
|
|
i2c-mux@75 {
|
|
compatible = "nxp,pca9548"; /* u22 */
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x75>;
|
|
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
|
|
i2c@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
/* FMCP_HSPC_IIC */
|
|
};
|
|
i2c_si570_user_c1: i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
|
|
#clock-cells = <0>;
|
|
compatible = "silabs,si570";
|
|
reg = <0x5d>;
|
|
temperature-stability = <50>;
|
|
factory-fout = <300000000>;
|
|
clock-frequency = <300000000>;
|
|
clock-output-names = "si570_user_c1";
|
|
};
|
|
};
|
|
i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
/* SYSMON */
|
|
};
|
|
i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
/* DDR4 SODIMM */
|
|
};
|
|
i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
/* SFP3 */
|
|
};
|
|
i2c@5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
/* SFP2 */
|
|
};
|
|
i2c@6 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <6>;
|
|
/* SFP1 */
|
|
};
|
|
i2c@7 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <7>;
|
|
/* SFP0 */
|
|
};
|
|
};
|
|
/* MSP430 */
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
is-dual = <1>;
|
|
flash@0 {
|
|
compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
|
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
|
};
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata {
|
|
status = "okay";
|
|
/* SATA OOB timing settings */
|
|
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
phy-names = "sata-phy";
|
|
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
|
|
};
|
|
|
|
/* SD1 with level shifter */
|
|
&sdhci1 {
|
|
status = "okay";
|
|
disable-wp;
|
|
/*
|
|
* This property should be removed for supporting UHS mode
|
|
*/
|
|
no-1-8-v;
|
|
xlnx,mio_bank = <1>;
|
|
};
|
|
|
|
&serdes {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* ULPI SMSC USB3320 */
|
|
&usb0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&dwc3_0 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
snps,usb3_lpm_capable;
|
|
phy-names = "usb3-phy";
|
|
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
|
|
};
|