776 lines
18 KiB
C
776 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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* Copyright (C) 2010 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clk.h>
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#include <log.h>
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#include <usb.h>
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#include <errno.h>
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#include <wait_bit.h>
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#include <asm/global_data.h>
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <usb/ehci-ci.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/sys_proto.h>
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#include <dm.h>
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#include <asm/mach-types.h>
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#include <power/regulator.h>
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#include <linux/usb/otg.h>
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#include "ehci.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define USB_OTGREGS_OFFSET 0x000
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#define USB_H1REGS_OFFSET 0x200
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#define USB_H2REGS_OFFSET 0x400
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#define USB_H3REGS_OFFSET 0x600
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#define USB_OTHERREGS_OFFSET 0x800
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#define USB_H1_CTRL_OFFSET 0x04
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#define USBPHY_CTRL 0x00000030
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#define USBPHY_CTRL_SET 0x00000034
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#define USBPHY_CTRL_CLR 0x00000038
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#define USBPHY_CTRL_TOG 0x0000003c
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#define USBPHY_PWD 0x00000000
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#define USBPHY_CTRL_SFTRST 0x80000000
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#define USBPHY_CTRL_CLKGATE 0x40000000
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#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
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#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
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#define USBPHY_CTRL_OTG_ID 0x08000000
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#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
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#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
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#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
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#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
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#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
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#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
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#define USBNC_OFFSET 0x200
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#define USBNC_PHY_STATUS_OFFSET 0x23C
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#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
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#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
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#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
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#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
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#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
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/* USBCMD */
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#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
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#define UCMD_RESET (1 << 1) /* controller reset */
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/* If this is not defined, assume MX6/MX7/MX8M SoC default */
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#ifndef CONFIG_MXC_USB_PORTSC
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#endif
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/* Base address for this IP block is 0x02184800 */
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struct usbnc_regs {
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u32 ctrl[4]; /* otg/host1-3 */
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u32 uh2_hsic_ctrl;
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u32 uh3_hsic_ctrl;
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u32 otg_phy_ctrl_0;
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u32 uh1_phy_ctrl_0;
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u32 reserve1[4];
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u32 phy_cfg1;
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u32 phy_cfg2;
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u32 reserve2;
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u32 phy_status;
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u32 reserve3[4];
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u32 adp_cfg1;
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u32 adp_cfg2;
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u32 adp_status;
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};
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#if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
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static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
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int anatop_bits_index)
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{
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void __iomem *chrg_detect;
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void __iomem *pll_480_ctrl_clr;
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void __iomem *pll_480_ctrl_set;
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if (!is_mx6())
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return;
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switch (anatop_bits_index) {
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case 0:
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chrg_detect = &anatop->usb1_chrg_detect;
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pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
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pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
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break;
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case 1:
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chrg_detect = &anatop->usb2_chrg_detect;
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pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
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pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
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break;
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default:
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return;
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}
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/*
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* Some phy and power's special controls
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* 1. The external charger detector needs to be disabled
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* or the signal at DP will be poor
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* 2. The PLL's power and output to usb
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* is totally controlled by IC, so the Software only needs
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* to enable them at initializtion.
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*/
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writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
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chrg_detect);
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writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
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pll_480_ctrl_clr);
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writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
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ANADIG_USB2_PLL_480_CTRL_POWER |
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ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
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pll_480_ctrl_set);
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}
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#else
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static void __maybe_unused
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usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
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#endif
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#if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
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static void usb_power_config_mx7(struct usbnc_regs *usbnc)
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{
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void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
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if (!is_mx7())
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return;
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/*
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* Clear the ACAENB to enable usb_otg_id detection,
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* otherwise it is the ACA detection enabled.
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*/
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clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
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}
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#else
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static void __maybe_unused
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usb_power_config_mx7(void *usbnc) { }
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#endif
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#if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
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static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
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{
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if (!is_mx7ulp())
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return;
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writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
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&usbphy->usb1_chrg_detect);
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scg_enable_usb_pll(true);
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}
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#else
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static void __maybe_unused
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usb_power_config_mx7ulp(void *usbphy) { }
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#endif
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
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static const unsigned phy_bases[] = {
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USB_PHY0_BASE_ADDR,
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#if defined(USB_PHY1_BASE_ADDR)
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USB_PHY1_BASE_ADDR,
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#endif
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};
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#if !defined(CONFIG_PHY)
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static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
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{
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phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
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writel(USBPHY_CTRL_CLKGATE, phy_reg);
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}
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/* Return 0 : host node, <>0 : device mode */
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static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
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{
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void __iomem *phy_ctrl;
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void __iomem *usb_cmd;
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int ret;
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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usb_cmd = (void __iomem *)&ehci->usbcmd;
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/* Stop then Reset */
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clrbits_le32(usb_cmd, UCMD_RUN_STOP);
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ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
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if (ret)
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return ret;
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setbits_le32(usb_cmd, UCMD_RESET);
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ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
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if (ret)
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return ret;
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/* Reset USBPHY module */
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setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Remove CLKGATE and SFTRST */
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clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Power up the PHY */
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writel(0, phy_reg + USBPHY_PWD);
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/* enable FS/LS device */
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setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
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USBPHY_CTRL_ENUTMILEVEL3);
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return 0;
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}
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#endif
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int usb_phy_mode(int port)
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{
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void __iomem *phy_reg;
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void __iomem *phy_ctrl;
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u32 val;
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phy_reg = (void __iomem *)phy_bases[port];
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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val = readl(phy_ctrl);
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if (val & USBPHY_CTRL_OTG_ID)
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return USB_INIT_DEVICE;
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else
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return USB_INIT_HOST;
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}
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#elif defined(CONFIG_MX7)
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int usb_phy_mode(int port)
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{
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * port) + USBNC_OFFSET);
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void __iomem *status = (void __iomem *)(&usbnc->phy_status);
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u32 val;
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val = readl(status);
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if (val & USBNC_PHYSTATUS_ID_DIG)
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return USB_INIT_DEVICE;
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else
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return USB_INIT_HOST;
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}
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#endif
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#if !defined(CONFIG_PHY)
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/* Should be done in the MXS PHY driver */
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static void usb_oc_config(struct usbnc_regs *usbnc, int index)
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{
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void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
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#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
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/* mx6qarm2 seems to required a different setting*/
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clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
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#else
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setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
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#endif
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setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
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/* Set power polarity to high active */
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#ifdef CONFIG_MXC_USB_OTG_HACTIVE
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setbits_le32(ctrl, UCTRL_PWR_POL);
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#else
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clrbits_le32(ctrl, UCTRL_PWR_POL);
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#endif
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}
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#endif
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#if !CONFIG_IS_ENABLED(DM_USB)
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/**
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* board_usb_phy_mode - override usb phy mode
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* @port: usb host/otg port
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*
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* Target board specific, override usb_phy_mode.
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* When usb-otg is used as usb host port, iomux pad usb_otg_id can be
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* left disconnected in this case usb_phy_mode will not be able to identify
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* the phy mode that usb port is used.
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* Machine file overrides board_usb_phy_mode.
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*
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* Return: USB_INIT_DEVICE or USB_INIT_HOST
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*/
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int __weak board_usb_phy_mode(int port)
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{
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return usb_phy_mode(port);
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}
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/**
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* board_ehci_hcd_init - set usb vbus voltage
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* @port: usb otg port
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*
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* Target board specific, setup iomux pad to setup supply vbus voltage
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* for usb otg port. Machine board file overrides board_ehci_hcd_init
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*
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* Return: 0 Success
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*/
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int __weak board_ehci_hcd_init(int port)
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{
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return 0;
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}
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/**
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* board_ehci_power - enables/disables usb vbus voltage
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* @port: usb otg port
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* @on: on/off vbus voltage
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*
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* Enables/disables supply vbus voltage for usb otg port.
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* Machine board file overrides board_ehci_power
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*
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* Return: 0 Success
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*/
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int __weak board_ehci_power(int port, int on)
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{
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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enum usb_init_type type;
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#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
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u32 controller_spacing = 0x200;
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struct anatop_regs __iomem *anatop =
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(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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USB_OTHERREGS_OFFSET);
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#elif defined(CONFIG_MX7)
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u32 controller_spacing = 0x10000;
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * index) + USBNC_OFFSET);
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#elif defined(CONFIG_MX7ULP)
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u32 controller_spacing = 0x10000;
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struct usbphy_regs __iomem *usbphy =
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(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * index) + USBNC_OFFSET);
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#endif
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struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
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(controller_spacing * index));
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int ret;
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if (index > 3)
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return -EINVAL;
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if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
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if (usb_fused((ulong)ehci)) {
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printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
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(ulong)ehci);
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return -ENODEV;
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}
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}
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enable_usboh3_clk(1);
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mdelay(1);
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/* Do board specific initialization */
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ret = board_ehci_hcd_init(index);
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if (ret) {
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enable_usboh3_clk(0);
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return ret;
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}
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#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT)
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usb_power_config_mx6(anatop, index);
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#elif defined (CONFIG_MX7)
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usb_power_config_mx7(usbnc);
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#elif defined (CONFIG_MX7ULP)
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usb_power_config_mx7ulp(usbphy);
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#endif
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usb_oc_config(usbnc, index);
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
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if (index < ARRAY_SIZE(phy_bases)) {
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usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1);
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usb_phy_enable(ehci, (void __iomem *)phy_bases[index]);
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}
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#endif
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type = board_usb_phy_mode(index);
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if (hccr && hcor) {
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*hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uintptr_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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}
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if ((type == init) || (type == USB_INIT_DEVICE))
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board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
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if (type != init)
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return -ENODEV;
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if (type == USB_INIT_DEVICE)
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return 0;
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setbits_le32(&ehci->usbmode, CM_HOST);
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writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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mdelay(10);
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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#else
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struct ehci_mx6_priv_data {
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struct ehci_ctrl ctrl;
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struct usb_ehci *ehci;
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struct udevice *vbus_supply;
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struct clk clk;
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struct phy phy;
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enum usb_init_type init_type;
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#if !defined(CONFIG_PHY)
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int portnr;
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void __iomem *phy_addr;
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void __iomem *misc_addr;
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void __iomem *anatop_addr;
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#endif
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};
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static int mx6_init_after_reset(struct ehci_ctrl *dev)
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{
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struct ehci_mx6_priv_data *priv = dev->priv;
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enum usb_init_type type = priv->init_type;
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struct usb_ehci *ehci = priv->ehci;
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#if !defined(CONFIG_PHY)
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usb_power_config_mx6(priv->anatop_addr, priv->portnr);
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usb_power_config_mx7(priv->misc_addr);
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usb_power_config_mx7ulp(priv->phy_addr);
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usb_oc_config(priv->misc_addr, priv->portnr);
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
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usb_internal_phy_clock_gate(priv->phy_addr, 1);
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usb_phy_enable(ehci, priv->phy_addr);
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#endif
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#endif
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->vbus_supply) {
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int ret;
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ret = regulator_set_enable(priv->vbus_supply,
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(type == USB_INIT_DEVICE) ?
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false : true);
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if (ret && ret != -ENOSYS) {
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printf("Error enabling VBUS supply (ret=%i)\n", ret);
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return ret;
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}
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}
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#endif
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if (type == USB_INIT_DEVICE)
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return 0;
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setbits_le32(&ehci->usbmode, CM_HOST);
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writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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setbits_le32(&ehci->portsc, USB_EN);
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mdelay(10);
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return 0;
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}
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|
|
static const struct ehci_ops mx6_ehci_ops = {
|
|
.init_after_reset = mx6_init_after_reset
|
|
};
|
|
|
|
static int ehci_usb_phy_mode(struct udevice *dev)
|
|
{
|
|
struct usb_plat *plat = dev_get_plat(dev);
|
|
void *__iomem addr = dev_read_addr_ptr(dev);
|
|
void *__iomem phy_ctrl, *__iomem phy_status;
|
|
const void *blob = gd->fdt_blob;
|
|
int offset = dev_of_offset(dev), phy_off;
|
|
u32 val;
|
|
|
|
/*
|
|
* About fsl,usbphy, Refer to
|
|
* Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
|
|
*/
|
|
if (is_mx6() || is_mx7ulp() || is_imxrt()) {
|
|
phy_off = fdtdec_lookup_phandle(blob,
|
|
offset,
|
|
"fsl,usbphy");
|
|
if (phy_off < 0)
|
|
return -EINVAL;
|
|
|
|
addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
|
|
"reg");
|
|
if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
|
|
val = readl(phy_ctrl);
|
|
|
|
if (val & USBPHY_CTRL_OTG_ID)
|
|
plat->init_type = USB_INIT_DEVICE;
|
|
else
|
|
plat->init_type = USB_INIT_HOST;
|
|
} else if (is_mx7()) {
|
|
phy_status = (void __iomem *)(addr +
|
|
USBNC_PHY_STATUS_OFFSET);
|
|
val = readl(phy_status);
|
|
|
|
if (val & USBNC_PHYSTATUS_ID_DIG)
|
|
plat->init_type = USB_INIT_DEVICE;
|
|
else
|
|
plat->init_type = USB_INIT_HOST;
|
|
} else {
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ehci_usb_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct usb_plat *plat = dev_get_plat(dev);
|
|
enum usb_dr_mode dr_mode;
|
|
|
|
dr_mode = usb_get_dr_mode(dev_ofnode(dev));
|
|
|
|
switch (dr_mode) {
|
|
case USB_DR_MODE_HOST:
|
|
plat->init_type = USB_INIT_HOST;
|
|
break;
|
|
case USB_DR_MODE_PERIPHERAL:
|
|
plat->init_type = USB_INIT_DEVICE;
|
|
break;
|
|
case USB_DR_MODE_OTG:
|
|
case USB_DR_MODE_UNKNOWN:
|
|
return ehci_usb_phy_mode(dev);
|
|
};
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mx6_parse_dt_addrs(struct udevice *dev)
|
|
{
|
|
#if !defined(CONFIG_PHY)
|
|
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
|
|
int phy_off, misc_off;
|
|
const void *blob = gd->fdt_blob;
|
|
int offset = dev_of_offset(dev);
|
|
void *__iomem addr;
|
|
|
|
phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy");
|
|
if (phy_off < 0) {
|
|
phy_off = fdtdec_lookup_phandle(blob, offset, "phys");
|
|
if (phy_off < 0)
|
|
return -EINVAL;
|
|
}
|
|
|
|
misc_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbmisc");
|
|
if (misc_off < 0)
|
|
return -EINVAL;
|
|
|
|
addr = (void __iomem *)fdtdec_get_addr(blob, phy_off, "reg");
|
|
if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
|
|
addr = NULL;
|
|
|
|
priv->phy_addr = addr;
|
|
|
|
addr = (void __iomem *)fdtdec_get_addr(blob, misc_off, "reg");
|
|
if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
priv->misc_addr = addr;
|
|
|
|
#if defined(CONFIG_MX6)
|
|
int anatop_off, ret, devnump;
|
|
|
|
ret = fdtdec_get_alias_seq(blob, dev->uclass->uc_drv->name,
|
|
phy_off, &devnump);
|
|
if (ret < 0)
|
|
return ret;
|
|
priv->portnr = devnump;
|
|
|
|
/* Resolve ANATOP offset through USB PHY node */
|
|
anatop_off = fdtdec_lookup_phandle(blob, phy_off, "fsl,anatop");
|
|
if (anatop_off < 0)
|
|
return -EINVAL;
|
|
|
|
addr = (void __iomem *)fdtdec_get_addr(blob, anatop_off, "reg");
|
|
if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
priv->anatop_addr = addr;
|
|
#endif
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static int ehci_usb_probe(struct udevice *dev)
|
|
{
|
|
struct usb_plat *plat = dev_get_plat(dev);
|
|
struct usb_ehci *ehci = dev_read_addr_ptr(dev);
|
|
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
|
|
enum usb_init_type type = plat->init_type;
|
|
struct ehci_hccr *hccr;
|
|
struct ehci_hcor *hcor;
|
|
int ret;
|
|
|
|
if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
|
|
if (usb_fused((ulong)ehci)) {
|
|
printf("SoC fuse indicates USB@0x%lx is unavailable.\n",
|
|
(ulong)ehci);
|
|
return -ENODEV;
|
|
}
|
|
}
|
|
|
|
ret = mx6_parse_dt_addrs(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
priv->ehci = ehci;
|
|
priv->init_type = type;
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
ret = clk_get_by_index(dev, 0, &priv->clk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = clk_enable(&priv->clk);
|
|
if (ret)
|
|
return ret;
|
|
#else
|
|
/* Compatibility with DM_USB and !CLK */
|
|
enable_usboh3_clk(1);
|
|
mdelay(1);
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
ret = device_get_supply_regulator(dev, "vbus-supply",
|
|
&priv->vbus_supply);
|
|
if (ret)
|
|
debug("%s: No vbus supply\n", dev->name);
|
|
#endif
|
|
|
|
#if !defined(CONFIG_PHY)
|
|
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
|
|
usb_power_config_mx7(priv->misc_addr);
|
|
usb_power_config_mx7ulp(priv->phy_addr);
|
|
|
|
usb_oc_config(priv->misc_addr, priv->portnr);
|
|
|
|
#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT)
|
|
usb_internal_phy_clock_gate(priv->phy_addr, 1);
|
|
usb_phy_enable(ehci, priv->phy_addr);
|
|
#endif
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
if (priv->vbus_supply) {
|
|
ret = regulator_set_enable(priv->vbus_supply,
|
|
(type == USB_INIT_DEVICE) ?
|
|
false : true);
|
|
if (ret && ret != -ENOSYS) {
|
|
printf("Error enabling VBUS supply (ret=%i)\n", ret);
|
|
goto err_clk;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
if (priv->init_type == USB_INIT_HOST) {
|
|
setbits_le32(&ehci->usbmode, CM_HOST);
|
|
writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
|
|
setbits_le32(&ehci->portsc, USB_EN);
|
|
}
|
|
|
|
mdelay(10);
|
|
|
|
#if defined(CONFIG_PHY)
|
|
ret = ehci_setup_phy(dev, &priv->phy, 0);
|
|
if (ret)
|
|
goto err_regulator;
|
|
#endif
|
|
|
|
hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
|
|
hcor = (struct ehci_hcor *)((uintptr_t)hccr +
|
|
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
|
|
|
|
ret = ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
|
|
if (ret)
|
|
goto err_phy;
|
|
|
|
return ret;
|
|
|
|
err_phy:
|
|
#if defined(CONFIG_PHY)
|
|
ehci_shutdown_phy(dev, &priv->phy);
|
|
err_regulator:
|
|
#endif
|
|
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
if (priv->vbus_supply)
|
|
regulator_set_enable(priv->vbus_supply, false);
|
|
err_clk:
|
|
#endif
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
clk_disable(&priv->clk);
|
|
#else
|
|
/* Compatibility with DM_USB and !CLK */
|
|
enable_usboh3_clk(0);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
int ehci_usb_remove(struct udevice *dev)
|
|
{
|
|
struct ehci_mx6_priv_data *priv __maybe_unused = dev_get_priv(dev);
|
|
|
|
ehci_deregister(dev);
|
|
|
|
#if defined(CONFIG_PHY)
|
|
ehci_shutdown_phy(dev, &priv->phy);
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
|
if (priv->vbus_supply)
|
|
regulator_set_enable(priv->vbus_supply, false);
|
|
#endif
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
clk_disable(&priv->clk);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id mx6_usb_ids[] = {
|
|
{ .compatible = "fsl,imx27-usb" },
|
|
{ .compatible = "fsl,imx7d-usb" },
|
|
{ .compatible = "fsl,imxrt-usb" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(usb_mx6) = {
|
|
.name = "ehci_mx6",
|
|
.id = UCLASS_USB,
|
|
.of_match = mx6_usb_ids,
|
|
.of_to_plat = ehci_usb_of_to_plat,
|
|
.probe = ehci_usb_probe,
|
|
.remove = ehci_usb_remove,
|
|
.ops = &ehci_usb_ops,
|
|
.plat_auto = sizeof(struct usb_plat),
|
|
.priv_auto = sizeof(struct ehci_mx6_priv_data),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|
|
#endif
|