mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
bea12b7823
Whilst U-boot does not require this itself, Linux currently relies upon it having been muxed and enabled by the bootloader. Thus in order to preserve compatibility with current kernels before a fix is merged in Linux we will enable the SERIRQ interrupt and mux it to its pin. Without doing this current kernels will never receive serial port interrupts and the end result is typically that userland appears to hang. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
68 lines
2.1 KiB
C
68 lines
2.1 KiB
C
/*
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* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 Imagination Technologies
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _MIPS_ASM_MALTA_H
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#define _MIPS_ASM_MALTA_H
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#define MALTA_GT_BASE 0x1be00000
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#define MALTA_GT_PCIIO_BASE 0x18000000
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#define MALTA_GT_UART0_BASE (MALTA_GT_PCIIO_BASE + 0x3f8)
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#define MALTA_MSC01_BIU_BASE 0x1bc80000
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#define MALTA_MSC01_PCI_BASE 0x1bd00000
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#define MALTA_MSC01_PBC_BASE 0x1bd40000
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#define MALTA_MSC01_IP1_BASE 0x1bc00000
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#define MALTA_MSC01_IP1_SIZE 0x00400000
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#define MALTA_MSC01_IP2_BASE1 0x10000000
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#define MALTA_MSC01_IP2_SIZE1 0x08000000
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#define MALTA_MSC01_IP2_BASE2 0x18000000
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#define MALTA_MSC01_IP2_SIZE2 0x04000000
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#define MALTA_MSC01_IP3_BASE 0x1c000000
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#define MALTA_MSC01_IP3_SIZE 0x04000000
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#define MALTA_MSC01_PCIMEM_BASE 0x10000000
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#define MALTA_MSC01_PCIMEM_SIZE 0x10000000
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#define MALTA_MSC01_PCIMEM_MAP 0x10000000
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#define MALTA_MSC01_PCIIO_BASE 0x1b000000
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#define MALTA_MSC01_PCIIO_SIZE 0x00800000
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#define MALTA_MSC01_PCIIO_MAP 0x00000000
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#define MALTA_MSC01_UART0_BASE (MALTA_MSC01_PCIIO_BASE + 0x3f8)
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#define MALTA_ASCIIWORD 0x1f000410
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#define MALTA_ASCIIPOS0 0x1f000418
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#define MALTA_ASCIIPOS1 0x1f000420
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#define MALTA_ASCIIPOS2 0x1f000428
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#define MALTA_ASCIIPOS3 0x1f000430
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#define MALTA_ASCIIPOS4 0x1f000438
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#define MALTA_ASCIIPOS5 0x1f000440
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#define MALTA_ASCIIPOS6 0x1f000448
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#define MALTA_ASCIIPOS7 0x1f000450
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#define MALTA_RESET_BASE 0x1f000500
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#define GORESET 0x42
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#define MALTA_FLASH_BASE 0x1e000000
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#define MALTA_REVISION 0x1fc00010
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#define MALTA_REVISION_CORID_SHF 10
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#define MALTA_REVISION_CORID_MSK (0x3f << MALTA_REVISION_CORID_SHF)
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#define MALTA_REVISION_CORID_CORE_LV 1
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#define MALTA_REVISION_CORID_CORE_FPGA6 14
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#define PCI_CFG_PIIX4_PIRQRCA 0x60
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#define PCI_CFG_PIIX4_PIRQRCB 0x61
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#define PCI_CFG_PIIX4_PIRQRCC 0x62
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#define PCI_CFG_PIIX4_PIRQRCD 0x63
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#define PCI_CFG_PIIX4_SERIRQC 0x64
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#define PCI_CFG_PIIX4_GENCFG 0xb0
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#define PCI_CFG_PIIX4_SERIRQC_EN (1 << 7)
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#define PCI_CFG_PIIX4_SERIRQC_CONT (1 << 6)
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#define PCI_CFG_PIIX4_GENCFG_SERIRQ (1 << 16)
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#endif /* _MIPS_ASM_MALTA_H */
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