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https://github.com/brain-hackers/u-boot-brain
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fa476f75bf
For boards such as the MIPS Malta with an FPGA core card it is desirable to be able to detect the L1 cache sizes at runtime, since they are not dependant upon the board but on the FPGA bitstream in use. This patch performs that detection when the CONFIG_SYS_[DI]CACHE_SIZE macros are not defined by the board configuration. In cases where the sizes are detected this patch also removes the restriction that the I-cache & D-cache line sizes must be the same, as this is not necessarily true. If the cache sizes are defined by a configuration then they will be hardcoded as before, so this patch will not add overhead to such boards. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
282 lines
6.2 KiB
ArmAsm
282 lines
6.2 KiB
ArmAsm
/*
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* Cache-handling routined for MIPS CPUs
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#ifndef CONFIG_SYS_MIPS_CACHE_MODE
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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#endif
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#define RA t9
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#define INDEX_BASE CKSEG0
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.macro cache_op op addr
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.set push
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.set noreorder
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.set mips3
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cache \op, 0(\addr)
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.set pop
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.endm
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
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#if LONGSIZE == 4
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LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
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#endif
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.endm
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/*
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* mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
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*/
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LEAF(mips_init_icache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear tag to invalidate */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op INDEX_STORE_TAG_I t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* fill once, so data field parity is correct */
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PTR_LI t0, INDEX_BASE
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2: cache_op FILL t0
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PTR_ADDU t0, a2
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bne t0, t1, 2b
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/* invalidate again - prudent but not strictly neccessary */
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PTR_LI t0, INDEX_BASE
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1: cache_op INDEX_STORE_TAG_I t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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END(mips_init_icache)
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/*
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* mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
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*/
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LEAF(mips_init_dcache)
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blez a1, 9f
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mtc0 zero, CP0_TAGLO
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op INDEX_STORE_TAG_D t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* load from each line (in cached space) */
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PTR_LI t0, INDEX_BASE
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2: LONG_L zero, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 2b
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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1: cache_op INDEX_STORE_TAG_D t0
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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END(mips_init_dcache)
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/*
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* mips_cache_reset - low level initialisation of the primary caches
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*
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* This routine initialises the primary caches to ensure that they have good
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* parity. It must be called by the ROM before any cached locations are used
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* to prevent the possibility of data with bad parity being written to memory.
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*
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* To initialise the instruction cache it is essential that a source of data
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* with good parity is available. This routine will initialise an area of
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* memory starting at location zero to be used as a source of parity.
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*
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* RETURNS: N/A
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*
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*/
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NESTED(mips_cache_reset, 0, ra)
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move RA, ra
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#if !defined(CONFIG_SYS_ICACHE_SIZE) || !defined(CONFIG_SYS_DCACHE_SIZE) || \
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!defined(CONFIG_SYS_CACHELINE_SIZE)
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/* read Config1 for use below */
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mfc0 t5, CP0_CONFIG, 1
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#endif
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#ifdef CONFIG_SYS_CACHELINE_SIZE
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li t7, CONFIG_SYS_CACHELINE_SIZE
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li t8, CONFIG_SYS_CACHELINE_SIZE
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#else
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/* Detect I-cache line size. */
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srl t8, t5, MIPS_CONF1_IL_SHIFT
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andi t8, t8, (MIPS_CONF1_IL >> MIPS_CONF1_IL_SHIFT)
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beqz t8, 1f
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li t6, 2
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sllv t8, t6, t8
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1: /* Detect D-cache line size. */
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srl t7, t5, MIPS_CONF1_DL_SHIFT
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andi t7, t7, (MIPS_CONF1_DL >> MIPS_CONF1_DL_SHIFT)
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beqz t7, 1f
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li t6, 2
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sllv t7, t6, t7
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1:
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#endif
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#ifdef CONFIG_SYS_ICACHE_SIZE
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li t2, CONFIG_SYS_ICACHE_SIZE
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#else
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/* Detect I-cache size. */
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srl t6, t5, MIPS_CONF1_IS_SHIFT
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andi t6, t6, (MIPS_CONF1_IS >> MIPS_CONF1_IS_SHIFT)
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li t4, 32
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xori t2, t6, 0x7
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beqz t2, 1f
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addi t6, t6, 1
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sllv t4, t4, t6
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1: /* At this point t4 == I-cache sets. */
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mul t2, t4, t8
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srl t6, t5, MIPS_CONF1_IA_SHIFT
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andi t6, t6, (MIPS_CONF1_IA >> MIPS_CONF1_IA_SHIFT)
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addi t6, t6, 1
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/* At this point t6 == I-cache ways. */
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mul t2, t2, t6
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#endif
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#ifdef CONFIG_SYS_DCACHE_SIZE
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li t3, CONFIG_SYS_DCACHE_SIZE
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#else
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/* Detect D-cache size. */
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srl t6, t5, MIPS_CONF1_DS_SHIFT
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andi t6, t6, (MIPS_CONF1_DS >> MIPS_CONF1_DS_SHIFT)
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li t4, 32
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xori t3, t6, 0x7
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beqz t3, 1f
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addi t6, t6, 1
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sllv t4, t4, t6
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1: /* At this point t4 == I-cache sets. */
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mul t3, t4, t7
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srl t6, t5, MIPS_CONF1_DA_SHIFT
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andi t6, t6, (MIPS_CONF1_DA >> MIPS_CONF1_DA_SHIFT)
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addi t6, t6, 1
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/* At this point t6 == I-cache ways. */
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mul t3, t3, t6
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#endif
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/* Determine the largest L1 cache size */
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#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
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#if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
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li v0, CONFIG_SYS_ICACHE_SIZE
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#else
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li v0, CONFIG_SYS_DCACHE_SIZE
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#endif
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#else
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move v0, t2
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sltu t1, t2, t3
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movn v0, t3, t1
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#endif
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/*
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* Now clear that much memory starting from zero.
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*/
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PTR_LI a0, CKSEG1
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PTR_ADDU a1, a0, v0
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2: PTR_ADDIU a0, 64
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f_fill64 a0, -64, zero
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bne a0, a1, 2b
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/*
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* The caches are probably in an indeterminate state,
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* so we force good parity into them by doing an
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* invalidate, load/fill, invalidate for each line.
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*/
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/*
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* Assume bottom of RAM will generate good parity for the cache.
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*/
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/*
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* Initialize the I-cache first,
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*/
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move a1, t2
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move a2, t8
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PTR_LA v1, mips_init_icache
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jalr v1
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/*
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* then initialize D-cache.
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*/
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move a1, t3
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move a2, t7
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PTR_LA v1, mips_init_dcache
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jalr v1
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jr RA
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END(mips_cache_reset)
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/*
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* dcache_status - get cache status
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*
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* RETURNS: 0 - cache disabled; 1 - cache enabled
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*
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*/
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LEAF(dcache_status)
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mfc0 t0, CP0_CONFIG
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li t1, CONF_CM_UNCACHED
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andi t0, t0, CONF_CM_CMASK
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move v0, zero
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beq t0, t1, 2f
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li v0, 1
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2: jr ra
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END(dcache_status)
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/*
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* dcache_disable - disable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_disable)
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mfc0 t0, CP0_CONFIG
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li t1, -8
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and t0, t0, t1
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ori t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_disable)
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/*
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* dcache_enable - enable cache
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*
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* RETURNS: N/A
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*
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*/
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LEAF(dcache_enable)
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mfc0 t0, CP0_CONFIG
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ori t0, CONF_CM_CMASK
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xori t0, CONF_CM_CMASK
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ori t0, CONFIG_SYS_MIPS_CACHE_MODE
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mtc0 t0, CP0_CONFIG
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jr ra
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END(dcache_enable)
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