mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
230fe9b202
Add code necessary to program the FPGA part of SoCFPGA from U-Boot
with an RBF blob. This patch also integrates the code into the
FPGA driver framework in U-Boot so it can be used via the 'fpga'
command.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
V2: Move the not-CPU specific stuff into drivers/fpga/ and base
this on the cleaned up altera FPGA support.
79 lines
1.7 KiB
C
79 lines
1.7 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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* All rights reserved.
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*
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* This file contains only support functions used also by the SoCFPGA
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* platform code, the real meat is located in drivers/fpga/socfpga.c .
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Timeout count */
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#define FPGA_TIMEOUT_CNT 0x1000000
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static struct socfpga_fpga_manager *fpgamgr_regs =
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(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
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/* Check whether FPGA Init_Done signal is high */
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static int is_fpgamgr_initdone_high(void)
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{
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unsigned long val;
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val = readl(&fpgamgr_regs->gpio_ext_porta);
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return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
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}
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/* Get the FPGA mode */
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int fpgamgr_get_mode(void)
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{
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unsigned long val;
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val = readl(&fpgamgr_regs->stat);
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return val & FPGAMGRREGS_STAT_MODE_MASK;
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}
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/* Check whether FPGA is ready to be accessed */
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int fpgamgr_test_fpga_ready(void)
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{
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/* Check for init done signal */
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if (!is_fpgamgr_initdone_high())
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return 0;
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/* Check again to avoid false glitches */
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if (!is_fpgamgr_initdone_high())
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return 0;
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
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return 0;
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return 1;
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}
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/* Poll until FPGA is ready to be accessed or timeout occurred */
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int fpgamgr_poll_fpga_ready(void)
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{
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unsigned long i;
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/* If FPGA is blank, wait till WD invoke warm reset */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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/* check for init done signal */
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if (!is_fpgamgr_initdone_high())
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continue;
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/* check again to avoid false glitches */
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if (!is_fpgamgr_initdone_high())
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continue;
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return 1;
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}
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return 0;
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}
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