mirror of
https://github.com/brain-hackers/u-boot-brain
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68e1747f9c
Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
31 lines
570 B
C
31 lines
570 B
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _RESET_MANAGER_H_
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#define _RESET_MANAGER_H_
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void reset_cpu(ulong addr);
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void reset_deassert_peripherals_handoff(void);
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struct socfpga_reset_manager {
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u32 status;
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u32 ctrl;
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u32 counts;
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u32 padding1;
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u32 mpu_mod_reset;
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u32 per_mod_reset;
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u32 per2_mod_reset;
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u32 brg_mod_reset;
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};
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
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#else
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
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#endif
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#endif /* _RESET_MANAGER_H_ */
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