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https://github.com/brain-hackers/u-boot-brain
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68e1747f9c
Consolidating reset code into reset_manager.c. Also separating reset configuration for virtual target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See <clsee@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
40 lines
759 B
C
40 lines
759 B
C
/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/reset_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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/*
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* Write the reset manager register to cause reset
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*/
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void reset_cpu(ulong addr)
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{
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/* request a warm reset */
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writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
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&reset_manager_base->ctrl);
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/*
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* infinite loop here as watchdog will trigger and reset
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* the processor
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*/
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while (1)
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;
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}
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/*
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* Release peripherals from reset based on handoff
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*/
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void reset_deassert_peripherals_handoff(void)
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{
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writel(0, &reset_manager_base->per_mod_reset);
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}
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