mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
c978b52410
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
13 lines
312 B
Makefile
13 lines
312 B
Makefile
#
|
|
# (C) Copyright 2007 - 2013 Tensilica, Inc.
|
|
# (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
|
|
#
|
|
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
|
|
CROSS_COMPILE ?= xtensa-linux-
|
|
PLATFORM_CPPFLAGS += -D__XTENSA__ -mlongcalls -mforce-no-pic \
|
|
-ffunction-sections -fdata-sections
|
|
|
|
LDFLAGS_FINAL += --gc-sections
|