mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 23:48:52 +09:00
187 lines
4.6 KiB
C
187 lines
4.6 KiB
C
/*
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* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/onenand.h>
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#include "vct.h"
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#define BURST_SIZE_WORDS 4
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static u16 ebi_nand_read_word(void __iomem *addr)
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{
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reg_write(EBI_CPU_IO_ACCS(EBI_BASE), (EXT_DEVICE_CHANNEL_2 | (u32)addr));
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ebi_wait();
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return reg_read(EBI_IO_ACCS_DATA(EBI_BASE)) >> 16;
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}
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static void ebi_nand_write_word(u16 data, void __iomem * addr)
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{
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ebi_wait();
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reg_write(EBI_IO_ACCS_DATA(EBI_BASE), (data << 16));
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reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
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EXT_DEVICE_CHANNEL_2 | EBI_CPU_WRITE | (u32)addr);
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ebi_wait();
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}
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/*
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* EBI initialization for OneNAND FLASH access
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*/
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int ebi_init_onenand(void)
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{
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reg_write(EBI_DEV1_CONFIG1(EBI_BASE), 0x83000);
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reg_write(EBI_DEV2_CONFIG1(EBI_BASE), 0x00403002);
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reg_write(EBI_DEV2_CONFIG2(EBI_BASE), 0x50);
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reg_write(EBI_DEV3_CONFIG1(EBI_BASE), 0x00403002);
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reg_write(EBI_DEV3_CONFIG2(EBI_BASE), 0x0); /* byte/word ordering */
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reg_write(EBI_DEV2_TIM1_RD1(EBI_BASE), 0x00504000);
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reg_write(EBI_DEV2_TIM1_RD2(EBI_BASE), 0x00001000);
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reg_write(EBI_DEV2_TIM1_WR1(EBI_BASE), 0x12002223);
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reg_write(EBI_DEV2_TIM1_WR2(EBI_BASE), 0x3FC02220);
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reg_write(EBI_DEV3_TIM1_RD1(EBI_BASE), 0x00504000);
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reg_write(EBI_DEV3_TIM1_RD2(EBI_BASE), 0x00001000);
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reg_write(EBI_DEV3_TIM1_WR1(EBI_BASE), 0x05001000);
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reg_write(EBI_DEV3_TIM1_WR2(EBI_BASE), 0x00010200);
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reg_write(EBI_DEV2_TIM_EXT(EBI_BASE), 0xFFF00000);
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reg_write(EBI_DEV2_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
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reg_write(EBI_DEV3_TIM_EXT(EBI_BASE), 0xFFF00000);
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reg_write(EBI_DEV3_EXT_ACC(EBI_BASE), 0x0FFFFFFF);
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/* prepare DMA configuration for EBI */
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reg_write(EBI_DEV3_FIFO_CONFIG(EBI_BASE), 0x0101ff00);
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/* READ only no byte order change, TAG 1 used */
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reg_write(EBI_DEV3_DMA_CONFIG2(EBI_BASE), 0x00000004);
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reg_write(EBI_TAG1_SYS_ID(EBI_BASE), 0x0); /* SCC DMA channel 0 */
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reg_write(EBI_TAG2_SYS_ID(EBI_BASE), 0x1);
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reg_write(EBI_TAG3_SYS_ID(EBI_BASE), 0x2);
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reg_write(EBI_TAG4_SYS_ID(EBI_BASE), 0x3);
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return 0;
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}
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static void *memcpy_16_from_onenand(void *dst, const void *src, unsigned int len)
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{
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void *ret = dst;
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u16 *d = dst;
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u16 *s = (u16 *)src;
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len >>= 1;
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while (len-- > 0)
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*d++ = ebi_nand_read_word(s++);
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return ret;
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}
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static void *memcpy_32_from_onenand(void *dst, const void *src, unsigned int len)
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{
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void *ret = dst;
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u32 *d = (u32 *)dst;
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u32 s = (u32)src;
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u32 bytes_per_block = BURST_SIZE_WORDS * sizeof(int);
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u32 n_blocks = len / bytes_per_block;
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u32 block = 0;
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u32 burst_word;
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for (block = 0; block < n_blocks; block++) {
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/* Trigger read channel 3 */
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reg_write(EBI_CPU_IO_ACCS(EBI_BASE),
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(EXT_DEVICE_CHANNEL_3 | (s + (block * bytes_per_block))));
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/* Poll status to see whether read has finished */
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ebi_wait();
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/* Squirrel the data away in a safe place */
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for (burst_word = 0; burst_word < BURST_SIZE_WORDS; burst_word++)
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*d++ = reg_read(EBI_IO_ACCS_DATA(EBI_BASE));
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}
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return ret;
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}
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static void *memcpy_16_to_onenand(void *dst, const void *src, unsigned int len)
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{
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void *ret = dst;
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u16 *d = dst;
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u16 *s = (u16 *)src;
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len >>= 1;
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while (len-- > 0)
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ebi_nand_write_word(*s++, d++);
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return ret;
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}
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static inline int onenand_bufferram_offset(struct mtd_info *mtd, int area)
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{
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struct onenand_chip *this = mtd->priv;
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if (ONENAND_CURRENT_BUFFERRAM(this)) {
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if (area == ONENAND_DATARAM)
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return mtd->writesize;
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if (area == ONENAND_SPARERAM)
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return mtd->oobsize;
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}
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return 0;
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}
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static int ebi_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
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unsigned char *buffer, int offset,
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size_t count)
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{
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struct onenand_chip *this = mtd->priv;
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void __iomem *bufferram;
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bufferram = this->base + area;
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bufferram += onenand_bufferram_offset(mtd, area);
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if (count < 4)
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memcpy_16_from_onenand(buffer, bufferram + offset, count);
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else
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memcpy_32_from_onenand(buffer, bufferram + offset, count);
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return 0;
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}
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static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
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const unsigned char *buffer, int offset,
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size_t count)
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{
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struct onenand_chip *this = mtd->priv;
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void __iomem *bufferram;
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bufferram = this->base + area;
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bufferram += onenand_bufferram_offset(mtd, area);
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memcpy_16_to_onenand(bufferram + offset, buffer, count);
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return 0;
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}
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int onenand_board_init(struct mtd_info *mtd)
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{
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struct onenand_chip *chip = mtd->priv;
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/*
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* Insert board specific OneNAND access functions
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*/
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chip->read_word = ebi_nand_read_word;
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chip->write_word = ebi_nand_write_word;
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chip->read_bufferram = ebi_read_bufferram;
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chip->write_bufferram = ebi_write_bufferram;
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return 0;
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}
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