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https://github.com/brain-hackers/u-boot-brain
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47d7e3b5eb
Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
48 lines
1018 B
C
48 lines
1018 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <linux/err.h>
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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static u64 sifive_clint_get_count(struct udevice *dev)
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{
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return readq((void __iomem *)MTIME_REG(dev->priv));
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}
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static const struct timer_ops sifive_clint_ops = {
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.get_count = sifive_clint_get_count,
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};
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static int sifive_clint_probe(struct udevice *dev)
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{
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dev->priv = dev_read_addr_ptr(dev);
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if (!dev->priv)
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return -EINVAL;
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return timer_timebase_fallback(dev);
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0" },
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{ }
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};
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U_BOOT_DRIVER(sifive_clint) = {
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.name = "sifive_clint",
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.id = UCLASS_TIMER,
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.of_match = sifive_clint_ids,
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.probe = sifive_clint_probe,
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.ops = &sifive_clint_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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