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https://github.com/brain-hackers/u-boot-brain
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bd294e43dc
Configure RX and TX bus-width values to use flexspi in octal I/O mode. If bus-widths are not specified, then single I/O mode is set by default. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
86 lines
1.1 KiB
Plaintext
86 lines
1.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160ARDB device tree source
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*
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* Author: Priyanka Jain <priyanka.jain@nxp.com>
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* Sriram Dash <sriram.dash@nxp.com>
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*
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* Copyright 2018 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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/ {
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model = "NXP Layerscape LX2160ARDB Board";
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compatible = "fsl,lx2160ardb", "fsl,lx2160a";
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aliases {
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spi0 = &fspi;
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};
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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mmc-hs200-1_8v;
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};
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&fspi {
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status = "okay";
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mt35xu512aba0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi-rx-bus-width = <8>;
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spi-tx-bus-width = <1>;
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};
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mt35xu512aba1: flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <1>;
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spi-rx-bus-width = <8>;
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spi-tx-bus-width = <1>;
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};
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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&i2c4 {
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status = "okay";
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rtc@51 {
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compatible = "pcf2127-rtc";
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reg = <0x51>;
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};
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};
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&sata0 {
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status = "okay";
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};
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&sata1 {
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status = "okay";
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};
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&sata2 {
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status = "okay";
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};
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&sata3 {
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status = "okay";
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};
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