mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-10 14:53:26 +09:00
![Stefan Roese](/assets/img/avatar_default.png)
This patch enables the use of the kwboot tool, to boot mainline U-Boot on the Marvell Armada XP/38x SoC's. This is done by returning to the SoC's BootROM after SPL has initialized the SDRAM. We need to make sure to not reconfigure the internal register space and MBARs. Otherwise the BootROM will not be able to continue after SPL jumps back to it. To use this feature, please don't forget to change the BOOT_FROM line in your board specfic kwbimage.cfg file this way: BOOT_FROM uart Tested on these Marvell eval boards: DB-MV784MP-GP - Armada XP DB-88F6820-GP - Armada 38x Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
78 lines
1.5 KiB
ArmAsm
78 lines
1.5 KiB
ArmAsm
/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
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ENTRY(save_boot_params)
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stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
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ldr r12, =CONFIG_SPL_BOOTROM_SAVE
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str sp, [r12]
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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ENTRY(return_to_bootrom)
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ldr r12, =CONFIG_SPL_BOOTROM_SAVE
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ldr sp, [r12]
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mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
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ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
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ENDPROC(return_to_bootrom)
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#else
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ENTRY(save_boot_params)
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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#endif
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/*
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* cache_inv - invalidate Cache line
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* r0 - dest
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*/
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.global cache_inv
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.type cache_inv, %function
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cache_inv:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c6, 1
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v6 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v6
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.type flush_l1_v6, %function
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flush_l1_v6:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v7 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v7
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.type flush_l1_v7, %function
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flush_l1_v7:
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stmfd sp!, {r1-r12}
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dmb /* @data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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dsb /* @data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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