mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 23:26:16 +09:00
f14ae4180a
This patch brings the lwmon5 board support up-to-date. Here a summary of the changes: lwmon5 board port related: - GPIO's changed to control the LSB transmitter - Reset USB PHY's upon power-up - Enable CAN upon power-up - USB init error workaround (errata CHIP_6) - EBC: Enable burstmode and modify the timings for the GDC memory - EBC: Speed up NOR flash timings lwmon5 board POST related: - Add FPGA memory test - Add GDC memory test - DSP POST reworked - SYSMON POST: Fix handling of negative temperatures - Add output for sysmon1 POST - HW-watchdog min. time test reworked Additionally some coding-style changes were done. Signed-off-by: Sascha Laue <sascha.laue@liebherr.com> Signed-off-by: Stefan Roese <sr@denx.de>
71 lines
1.8 KiB
C
71 lines
1.8 KiB
C
/*
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* (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
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*
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* Developed for DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_DSP
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#include <asm/io.h>
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/* This test verifies DSP status bits in FPGA */
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DECLARE_GLOBAL_DATA_PTR;
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#define DSP_STATUS_REG 0xC4000008
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#define FPGA_STATUS_REG 0xC400000C
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int dsp_post_test(int flags)
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{
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uint old_value;
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uint read_value;
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int ret;
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/* momorize fpga status */
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old_value = in_be32((void *)FPGA_STATUS_REG);
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/* enable outputs */
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out_be32((void *)FPGA_STATUS_REG, 0x30);
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/* generate sync signal */
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out_be32((void *)DSP_STATUS_REG, 0x300);
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udelay(5);
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out_be32((void *)DSP_STATUS_REG, 0);
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udelay(500);
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/* read status */
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ret = 0;
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read_value = in_be32((void *)DSP_STATUS_REG) & 0x3;
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if (read_value != 0x03) {
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post_log("\nDSP status read %08X\n", read_value);
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ret = 1;
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}
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/* restore fpga status */
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out_be32((void *)FPGA_STATUS_REG, old_value);
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_DSP */
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