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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
468ec2f3ef
The K3 R5F remoteproc driver in U-Boot was upstreamed prior to the equivalent remoteproc driver in the Linux kernel. Some of the DT properties used in U-Boot got upstreamed using different names in Linux kernel. The modified property names include the R5F cluster mode configuration property "lockstep-mode"; and three different individual R5F core config properties - "atcm-enable", "btcm-enable" and "loczrama". The property names were updated as follows: lockstep-mode => ti,cluster-mode atcm-enable => ti,atcm-enable btcm-enable => ti,btcm-enable loczrama => ti,loczrama Update the K3 R5F remoteproc driver, the corresponding binding, and all the existing usage in AM65x, J721E and J7200 dts files all at once to use the new properties and to not break any bisectability. Signed-off-by: Suman Anna <s-anna@ti.com>
313 lines
7.7 KiB
Plaintext
313 lines
7.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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dmsc: dmsc@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes= <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x0 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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chipid: chipid@43000014 {
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compatible = "ti,am654-chipid";
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reg = <0x0 0x43000014 0x0 0x4>;
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};
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x100000>;
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ranges = <0x0 0x00 0x41c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 287 2>;
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clock-names = "fclk";
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};
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wkup_i2c0: i2c@42120000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x42120000 0x0 0x100>;
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interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 197 1>;
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power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 2>;
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clock-names = "fclk";
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};
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fss: system-controller@47000000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x47000000 0x0 0x100>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hbmc_mux: hbmc-mux {
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compatible = "mmio-mux";
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#mux-control-cells = <1>;
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mux-reg-masks = <0x4 0x2>; /* HBMC select */
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};
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hbmc: hyperbus@47034000 {
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compatible = "ti,am654-hbmc";
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reg = <0x0 0x47034000 0x0 0x100>,
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<0x5 0x00000000 0x1 0x0000000>;
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power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <2>;
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#size-cells = <1>;
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mux-controls = <&hbmc_mux 0>;
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clocks = <&k3_clks 102 5>;
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assigned-clocks = <&k3_clks 102 5>;
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assigned-clock-rates = <333333333>;
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};
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b00000 0x0 0x100>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 194 1>;
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power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
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};
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mcu_i2c1: i2c@40b10000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x0 0x40b10000 0x0 0x100>;
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interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "fck";
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clocks = <&k3_clks 195 1>;
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power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
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};
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cbass_mcu_navss: mcu-navss {
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compatible = "simple-mfd";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dma-coherent;
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dma-ranges;
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ti,sci-dev-id = <232>;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <235>;
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};
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mcu_udmap: dma-controller@285c0000 {
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compatible = "ti,j721e-navss-mcu-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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#dma-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <236>;
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ti,ringacc = <&mcu_ringacc>;
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ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
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<0x0f>; /* TX_HCHAN */
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ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
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<0x0b>; /* RX_HCHAN */
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ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
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};
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};
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x42110000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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ti,ngpio = <84>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 113 0>;
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clock-names = "gpio";
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};
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mcu_conf: scm_conf@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg = <0x4040 0x4>;
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reg-names = "gmii-sel";
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#phy-cells = <1>;
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};
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};
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mcu_cpsw: ethernet@46000000 {
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compatible = "ti,j721e-cpsw-nuss";
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x46000000 0x0 0x200000>;
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reg-names = "cpsw_nuss";
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ranges;
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dma-coherent;
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clocks = <&k3_clks 18 21>;
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clock-names = "fck";
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power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
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dmas = <&mcu_udmap 0xf000>,
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<&mcu_udmap 0xf001>,
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<&mcu_udmap 0xf002>,
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<&mcu_udmap 0xf003>,
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<&mcu_udmap 0xf004>,
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<&mcu_udmap 0xf005>,
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<&mcu_udmap 0xf006>,
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<&mcu_udmap 0xf007>,
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<&mcu_udmap 0x7000>;
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dma-names = "tx0", "tx1", "tx2", "tx3",
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"tx4", "tx5", "tx6", "tx7",
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"rx";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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cpsw_port1: port@1 {
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reg = <1>;
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ti,mac-only;
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ti,label = "port1";
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ti,syscon-efuse = <&mcu_conf 0x200>;
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phys = <&phy_gmii_sel 1>;
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};
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};
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davinci_mdio: mdio@f00 {
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compatible = "ti,cpsw-mdio","ti,davinci_mdio";
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reg = <0x0 0xf00 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 18 21>;
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clock-names = "fck";
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bus_freq = <1000000>;
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};
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cpts {
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clocks = <&k3_clks 18 2>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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};
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};
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mcu_r5fss0: r5fss@41000000 {
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compatible = "ti,j7200-r5fss";
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ti,cluster-mode = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x41000000 0x00 0x41000000 0x20000>,
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<0x41400000 0x00 0x41400000 0x20000>;
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power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
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mcu_r5fss0_core0: r5f@41000000 {
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compatible = "ti,j7200-r5f";
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reg = <0x41000000 0x00010000>,
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<0x41010000 0x00010000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <250>;
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ti,sci-proc-ids = <0x01 0xff>;
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resets = <&k3_reset 250 1>;
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firmware-name = "j7200-mcu-r5f0_0-fw";
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
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};
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mcu_r5fss0_core1: r5f@41400000 {
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compatible = "ti,j7200-r5f";
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reg = <0x41400000 0x00008000>,
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<0x41410000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <251>;
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ti,sci-proc-ids = <0x02 0xff>;
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resets = <&k3_reset 251 1>;
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firmware-name = "j7200-mcu-r5f0_1-fw";
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
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};
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};
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};
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