mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-15 15:46:16 +09:00
067716bac5
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: Heiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: Paul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: "Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Chin Liang See <clsee@altera.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Paul Kocialkowski <contact@paulk.fr>
143 lines
3.8 KiB
C
143 lines
3.8 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_RK3288_COMMON_H
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#define __CONFIG_RK3288_COMMON_H
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#include <asm/arch/hardware.h>
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_MALLOC_LEN (32 << 20)
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_SYS_THUMB_BUILD
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
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#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
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#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_SPL_BOARD_INIT
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#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
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/* Bootrom will load u-boot binary to 0x0 once return from SPL */
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x00100000
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#endif
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#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
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#define CONFIG_SYS_LOAD_ADDR 0x00800800
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#define CONFIG_SPL_STACK 0xff718000
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#define CONFIG_SPL_TEXT_BASE 0xff704004
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#define CONFIG_SILENT_CONSOLE
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#ifndef CONFIG_SPL_BUILD
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# define CONFIG_SYS_CONSOLE_IS_IN_ENV
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# define CONFIG_CONSOLE_MUX
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#endif
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/* MMC/SD IP block */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DWMMC
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_FAT_WRITE
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#define CONFIG_PARTITION_UUIDS
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#define CONFIG_CMD_PART
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/* RAW SD card / eMMC locations. */
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10)
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/* FAT sd card locations. */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_PINCTRL_SUPPORT
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#define CONFIG_SPL_RAM_SUPPORT
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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#define CONFIG_SYS_SDRAM_BASE 0
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#define CONFIG_NR_DRAM_BANKS 1
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#define SDRAM_BANK_SIZE (2UL << 30)
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#ifndef CONFIG_SPL_BUILD
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/* usb otg */
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#define CONFIG_USB_GADGET
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#define CONFIG_USB_GADGET_DUALSPEED
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#define CONFIG_USB_GADGET_DWC2_OTG
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#define CONFIG_ROCKCHIP_USB2_PHY
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#define CONFIG_USB_GADGET_VBUS_DRAW 0
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/* fastboot */
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#define CONFIG_CMD_FASTBOOT
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#define CONFIG_USB_FUNCTION_FASTBOOT
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#define CONFIG_FASTBOOT_FLASH
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#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */
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#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
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#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
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/* usb mass storage */
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#define CONFIG_USB_FUNCTION_MASS_STORAGE
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#define CONFIG_CMD_USB_MASS_STORAGE
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#define CONFIG_USB_GADGET_DOWNLOAD
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#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
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#define CONFIG_G_DNL_VENDOR_NUM 0x2207
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#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
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/* Enable gpt partition table */
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#define CONFIG_CMD_GPT
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#include <config_distro_defaults.h>
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#define ENV_MEM_LAYOUT_SETTINGS \
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"scriptaddr=0x00000000\0" \
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"pxefile_addr_r=0x00100000\0" \
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"fdt_addr_r=0x01f00000\0" \
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"kernel_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x04000000\0"
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#define CONFIG_RANDOM_UUID
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#define PARTS_DEFAULT \
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"uuid_disk=${uuid_gpt_disk};" \
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"name=boot,start=8M,size=64M,bootable,uuid=${uuid_gpt_boot};" \
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"name=rootfs,size=-,uuid=${uuid_gpt_rootfs};\0" \
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/* First try to boot from SD (index 0), then eMMC (index 1 */
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(MMC, mmc, 1)
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#include <config_distro_bootcmd.h>
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/* Linux fails to load the fdt if it's loaded above 512M on a Rock 2 board, so
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* limit the fdt reallocation to that */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x1fffffff\0" \
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"initrd_high=0x1fffffff\0" \
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"partitions=" PARTS_DEFAULT \
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ENV_MEM_LAYOUT_SETTINGS \
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ROCKCHIP_DEVICE_SETTINGS \
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BOOTENV
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#endif
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#endif
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