mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 07:06:19 +09:00
f749db3a75
LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
101 lines
1.7 KiB
C
101 lines
1.7 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <libfdt.h>
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#include <fsl_mc.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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init_final_memctl_regs();
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return 0;
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}
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int board_early_init_f(void)
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{
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init_early_memctl_regs(); /* tighten IFC timing */
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return 0;
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}
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int dram_init(void)
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{
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printf("DRAM: ");
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gd->ram_size = initdram(0);
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return 0;
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}
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int timer_init(void)
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{
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u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
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u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
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out_le32(cltbenr, 0x1); /* enable cluster0 timebase */
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out_le32(cntcr, 0x1); /* enable clock for timer */
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return 0;
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(ulong addr)
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{
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}
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int board_eth_init(bd_t *bis)
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{
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int error = 0;
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#ifdef CONFIG_SMC91111
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error = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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error = cpu_eth_init(bis);
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#endif
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return error;
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}
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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offset = fdt_path_offset(fdt, "/fsl,dprc@0");
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if (get_mc_boot_status() == 0)
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fdt_status_okay(fdt, offset);
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else
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fdt_status_fail(fdt, offset);
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}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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/* limit the memory size to bank 1 until Linux can handle 40-bit PA */
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_FSL_MC_ENET
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fdt_fixup_board_enet(blob);
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#endif
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}
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#endif
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