mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
e7dcf5645f
This header file is now only used by files that access internal environment features. Drop it from various places where it is not needed. Acked-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org>
435 lines
9.6 KiB
C
435 lines
9.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 samtec automotive software & electronics gmbh
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* Copyright (C) 2017-2019 softing automotive electronics gmbH
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*
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* Author: Christoph Fritz <chf.fritz@googlemail.com>
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <env.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze100_pmic.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include <pwm.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm
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#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
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PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \
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PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm)
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#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
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#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST)
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#define USDHC_RESET_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm)
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#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_PKE)
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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return 0;
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}
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
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MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
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MUX_MODE_SION,
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/* LAN8720 PHY Reset */
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MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const pwm_led_pads[] = {
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MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
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MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
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MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
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};
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#define PHY_RESET IMX_GPIO_NR(5, 9)
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int board_eth_init(bd_t *bis)
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{
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struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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unsigned char eth1addr[6];
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/* just to get secound mac address */
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imx_get_mac_from_fuse(1, eth1addr);
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if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
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eth_env_set_enetaddr("eth1addr", eth1addr);
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imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
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/*
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* Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
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* ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
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* ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
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*/
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clrsetbits_le32(&iomuxc_regs->gpr[1],
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IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
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IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
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IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(0, ENET_50MHZ);
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if (ret)
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goto eth_fail;
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/* reset phy */
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gpio_request(PHY_RESET, "PHY-reset");
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gpio_direction_output(PHY_RESET, 0);
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mdelay(16);
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gpio_set_value(PHY_RESET, 1);
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mdelay(1);
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ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
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IMX_FEC_BASE);
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if (ret)
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goto eth_fail;
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return ret;
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eth_fail:
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printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
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gpio_set_value(PHY_RESET, 0);
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return ret;
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}
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC */
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
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.gp = IMX_GPIO_NR(1, 0),
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},
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.sda = {
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.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
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.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
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.gp = IMX_GPIO_NR(1, 1),
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},
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};
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static struct pmic *pfuze_init(unsigned char i2cbus)
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{
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struct pmic *p;
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int ret;
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u32 reg;
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ret = power_pfuze100_init(i2cbus);
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if (ret)
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return NULL;
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p = pmic_get("PFUZE100");
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ret = pmic_probe(p);
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if (ret)
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return NULL;
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pmic_reg_read(p, PFUZE100_DEVICEID, ®);
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printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
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/* Set SW1AB stanby volage to 0.975V */
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pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
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reg &= ~SW1x_STBY_MASK;
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reg |= SW1x_0_975V;
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pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
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/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
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reg &= ~SW1xCONF_DVSSPEED_MASK;
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reg |= SW1xCONF_DVSSPEED_4US;
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pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
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/* Set SW1C standby voltage to 0.975V */
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pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
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reg &= ~SW1x_STBY_MASK;
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reg |= SW1x_0_975V;
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pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
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/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
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pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
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reg &= ~SW1xCONF_DVSSPEED_MASK;
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reg |= SW1xCONF_DVSSPEED_4US;
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pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
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return p;
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}
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static int pfuze_mode_init(struct pmic *p, u32 mode)
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{
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unsigned char offset, i, switch_num;
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u32 id;
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int ret;
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pmic_reg_read(p, PFUZE100_DEVICEID, &id);
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id = id & 0xf;
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if (id == 0) {
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switch_num = 6;
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offset = PFUZE100_SW1CMODE;
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} else if (id == 1) {
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switch_num = 4;
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offset = PFUZE100_SW2MODE;
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} else {
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printf("Not supported, id=%d\n", id);
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return -EINVAL;
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}
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ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
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if (ret < 0) {
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printf("Set SW1AB mode error!\n");
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return ret;
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}
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for (i = 0; i < switch_num - 1; i++) {
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ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
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if (ret < 0) {
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printf("Set switch 0x%x mode error!\n",
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offset + i * SWITCH_SIZE);
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return ret;
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}
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}
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return ret;
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}
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int power_init_board(void)
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{
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struct pmic *p;
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int ret;
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p = pfuze_init(I2C_PMIC);
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if (!p)
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return -ENODEV;
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ret = pfuze_mode_init(p, APS_PFM);
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if (ret < 0)
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return ret;
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return 0;
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}
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#ifdef CONFIG_USB_EHCI_MX6
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static iomux_v3_cfg_t const usb_otg_pads[] = {
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/* OGT1 */
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MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* OTG2 */
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MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
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};
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static void setup_iomux_usb(void)
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{
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imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
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ARRAY_SIZE(usb_otg_pads));
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}
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int board_usb_phy_mode(int port)
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{
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if (port == 1)
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return USB_INIT_HOST;
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else
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return usb_phy_mode(port);
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}
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#endif
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#ifdef CONFIG_PWM_IMX
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static int set_pwm_leds(void)
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{
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int ret;
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imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
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ARRAY_SIZE(pwm_led_pads));
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/* enable backlight PWM 2, green LED */
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ret = pwm_init(1, 0, 0);
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if (ret)
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goto error;
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/* duty cycle 200ns, period: 8000ns */
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ret = pwm_config(1, 200, 8000);
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if (ret)
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goto error;
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ret = pwm_enable(1);
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if (ret)
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goto error;
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/* enable backlight PWM 1, blue LED */
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ret = pwm_init(0, 0, 0);
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if (ret)
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goto error;
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/* duty cycle 200ns, period: 8000ns */
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ret = pwm_config(0, 200, 8000);
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if (ret)
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goto error;
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ret = pwm_enable(0);
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if (ret)
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goto error;
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/* enable backlight PWM 6, red LED */
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ret = pwm_init(5, 0, 0);
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if (ret)
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goto error;
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/* duty cycle 200ns, period: 8000ns */
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ret = pwm_config(5, 200, 8000);
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if (ret)
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goto error;
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ret = pwm_enable(5);
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error:
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return ret;
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}
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#else
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static int set_pwm_leds(void)
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{
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return 0;
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}
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#endif
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#define ADCx_HC0 0x00
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#define ADCx_HS 0x08
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#define ADCx_HS_C0 BIT(0)
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#define ADCx_R0 0x0c
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#define ADCx_CFG 0x14
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#define ADCx_CFG_SWMODE 0x308
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#define ADCx_GC 0x18
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#define ADCx_GC_CAL BIT(7)
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static int read_adc(u32 *val)
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{
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int ret;
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void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
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/* use software mode */
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writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
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/* start auto calibration */
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setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
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ret = wait_for_bit_le32(b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
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if (ret)
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goto adc_exit;
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/* start conversion */
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writel(0, b + ADCx_HC0);
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/* wait for conversion */
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ret = wait_for_bit_le32(b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
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if (ret)
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goto adc_exit;
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/* read result */
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*val = readl(b + ADCx_R0);
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adc_exit:
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if (ret)
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printf("ADC failure (ret=%i)\n", ret);
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unmap_physmem(b, MAP_NOCACHE);
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return ret;
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}
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#define VAL_UPPER 2498
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#define VAL_LOWER 1550
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static int set_pin_state(void)
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{
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u32 val;
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int ret;
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ret = read_adc(&val);
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if (ret)
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return ret;
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if (val >= VAL_UPPER)
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env_set("pin_state", "connected");
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else if (val < VAL_UPPER && val > VAL_LOWER)
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env_set("pin_state", "open");
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else
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env_set("pin_state", "button");
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return ret;
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}
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int board_late_init(void)
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{
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int ret;
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ret = set_pwm_leds();
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if (ret)
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return ret;
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ret = set_pin_state();
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return ret;
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}
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int board_early_init_f(void)
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{
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setup_iomux_usb();
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_SYS_I2C_MXC
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setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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#endif
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: VIN|ING 2000\n");
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return 0;
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}
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