mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
13b2ba1a11
The current GPL only licensing on the device trees makes it very impractical for other software components licensed under another license. To make it easier to reuse them, the device trees for UniPhier SoCs and boards have already been dual-licensed in Linux. Follow this trend in U-boot too. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
163 lines
3.4 KiB
Plaintext
163 lines
3.4 KiB
Plaintext
/*
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* Device Tree Source for UniPhier PH1-sLD8 SoC
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*
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* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+ X11
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "socionext,ph1-sld8";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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};
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clocks {
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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extbus: extbus {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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};
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uart0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x20>;
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clock-frequency = <80000000>;
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};
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uart1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x20>;
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clock-frequency = <80000000>;
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};
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uart2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x20>;
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clock-frequency = <80000000>;
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};
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uart3: serial@54006b00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006b00 0x20>;
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clock-frequency = <80000000>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58400000 0x40>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58480000 0x40>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58500000 0x40>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x58580000 0x40>;
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clock-frequency = <100000>;
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status = "disabled";
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};
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system-bus-controller-misc@59800000 {
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compatible = "socionext,uniphier-system-bus-controller-misc",
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"syscon";
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reg = <0x59800000 0x2000>;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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};
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timer@60000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x60000200 0x20>;
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interrupts = <1 11 0x104>;
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clocks = <&arm_timer_clk>;
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};
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timer@60000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x60000600 0x20>;
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interrupts = <1 13 0x104>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@60001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x60001000 0x1000>,
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<0x60000100 0x100>;
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};
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nand: nand@68000000 {
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compatible = "denali,denali-nand-dt";
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reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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reg-names = "nand_data", "denali_reg";
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};
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};
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};
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