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https://github.com/brain-hackers/u-boot-brain
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25ddd1fb0a
CONFIG_SYS_GBL_DATA_SIZE has always been just a bad workarond for not being able to use "sizeof(struct global_data)" in assembler files. Recent experience has shown that manual synchronization is not reliable enough. This patch renames CONFIG_SYS_GBL_DATA_SIZE into GENERATED_GBL_DATA_SIZE which gets automatically generated by the asm-offsets tool. In the result, all definitions of this value can be deleted from the board config files. We have to make sure that all files that reference such data include the new <asm-offsets.h> file. No other changes have been done yet, but it is obvious that similar changes / simplifications can be done for other, related macro definitions as well. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
194 lines
6.1 KiB
C
194 lines
6.1 KiB
C
/*
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* Configuation settings for the Renesas Technology R0P7785LC0011RL board
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*
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* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __SH7785LCR_H
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#define __SH7785LCR_H
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#undef DEBUG
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#define CONFIG_SH 1
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#define CONFIG_SH4A 1
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#define CONFIG_CPU_SH7785 1
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#define CONFIG_SH7785LCR 1
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_DFL
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#define CONFIG_CMD_SDRAM
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_USB
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#define CONFIG_USB_STORAGE
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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#define CONFIG_MAC_PARTITION
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootdevice=0:1\0" \
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"usbload=usb reset;usbboot;usb stop;bootm\0"
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#define CONFIG_VERSION_VARIABLE
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* MEMORY */
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#if defined(CONFIG_SH_32BIT)
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/* 0x40000000 - 0x47FFFFFF does not use */
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#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
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#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
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#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
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#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
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#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
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#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
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#define SH7785LCR_USB_BASE (0xa6000000)
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#else
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#define SH7785LCR_SDRAM_BASE (0x08000000)
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#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
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#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
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#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
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#define SH7785LCR_USB_BASE (0xb4000000)
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#endif
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "=> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE 512
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
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/* SCIF */
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#define CONFIG_SCIF_CONSOLE 1
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#define CONFIG_CONS_SCIF1 1
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#define CONFIG_SCIF_EXT_CLOCK 1
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#undef CONFIG_SYS_CONSOLE_INFO_QUIET
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#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
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#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
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#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
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(SH7785LCR_SDRAM_SIZE) - \
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4 * 1024 * 1024)
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#undef CONFIG_SYS_ALT_MEMTEST
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#undef CONFIG_SYS_MEMTEST_SCRATCH
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* FLASH */
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
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(0 * SH7785LCR_FLASH_BANK_SIZE) }
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
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#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
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#undef CONFIG_SYS_FLASH_PROTECTION
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#undef CONFIG_SYS_DIRECT_FLASH_TFTP
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/* R8A66597 */
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#define CONFIG_USB_R8A66597_HCD
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#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
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#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
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#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
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#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
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/* PCI Controller */
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#define CONFIG_PCI
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#define CONFIG_SH4_PCI
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#define CONFIG_SH7780_PCI
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#if defined(CONFIG_SH_32BIT)
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#define CONFIG_SH7780_PCI_LSR 0x1ff00001
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#define CONFIG_SH7780_PCI_LAR 0x5f000000
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#define CONFIG_SH7780_PCI_BAR 0x5f000000
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#else
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#define CONFIG_SH7780_PCI_LSR 0x07f00001
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#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
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#endif
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#define CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW 1
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#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
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#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
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#if defined(CONFIG_SH_32BIT)
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#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
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#else
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#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
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#endif
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#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
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/* Network device (RTL8169) support */
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#define CONFIG_NET_MULTI
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#define CONFIG_RTL8169
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/* ENV setting */
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SECT_SIZE (256 * 1024)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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/* Board Clock */
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/* The SCIF used external clock. system clock only used timer. */
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#define CONFIG_SYS_CLK_FREQ 50000000
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#define CONFIG_SYS_TMU_CLK_DIV 4
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#define CONFIG_SYS_HZ 1000
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#endif /* __SH7785LCR_H */
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