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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
287 lines
6.5 KiB
C
287 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Board initialization for EP93xx
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*
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* Copyright (C) 2013
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* Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
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*
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* Copyright (C) 2009
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* Matthias Kaehlcke <matthias <at> kaehlcke.net>
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*
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* (C) Copyright 2002 2003
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* Network Audio Technologies, Inc. <www.netaudiotech.com>
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* Adam Bezanson <bezanson <at> netaudiotech.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/arch/ep93xx.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* usb_div: 4, nbyp2: 1, pll2_en: 1
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* pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
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* pll2_x2: 384000000.000000, pll2_out: 192000000.000000
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*/
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#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
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24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
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1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
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SYSCON_CLKSET2_PLL2_EN | \
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SYSCON_CLKSET2_NBYP2 | \
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3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
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#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
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SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
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1 << SMC_BCR_MW_SHIFT)
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/* delay execution before timers are initialized */
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static inline void early_udelay(uint32_t usecs)
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{
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/* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
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register uint32_t loops = (usecs * 1000) / 20;
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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"bne 1b" : "=r" (loops) : "0" (loops));
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}
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#ifndef CONFIG_EP93XX_NO_FLASH_CFG
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static void flash_cfg(void)
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{
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struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
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writel(SMC_BCR6_VALUE, &smc->bcr6);
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}
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#else
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#define flash_cfg()
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#endif
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int board_init(void)
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{
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/*
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* Setup PLL2, PPL1 has been set during lowlevel init
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*/
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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writel(CLKSET2_VAL, &syscon->clkset2);
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/*
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* the user's guide recommends to wait at least 1 ms for PLL2 to
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* stabilize
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*/
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early_udelay(1000);
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/* Go to Async mode */
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__asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
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__asm__ volatile ("orr r0, r0, #0xc0000000");
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__asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
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icache_enable();
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#ifdef USE_920T_MMU
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dcache_enable();
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#endif
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/* Machine number, as defined in linux/arch/arm/tools/mach-types */
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gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* We have a console */
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gd->have_console = 1;
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enable_interrupts();
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flash_cfg();
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green_led_on();
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red_led_off();
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return 0;
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}
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int board_early_init_f(void)
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{
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/*
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* set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
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* 14.7456/2 MHz
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*/
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
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return 0;
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}
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int board_eth_init(bd_t *bd)
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{
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return ep93xx_eth_initialize(0, MAC_BASE);
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}
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static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
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unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
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{
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if (dram_bank_cnt == 1) {
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dram_bank_base[0] = PHYS_SDRAM_1;
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} else {
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/* Table lookup for holes in address space. Maximum memory
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* for the single SDCS may be up to 256Mb. We start scanning
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* banks from 1Mb, so it could be up to 128 banks theoretically.
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* We need at maximum 7 bits for the loockup, 8 slots is
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* enough for the worst case.
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*/
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unsigned tbl[8];
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unsigned i = dram_bank_cnt / 2;
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unsigned j = 0x00100000; /* 1 Mb */
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unsigned *ptbl = tbl;
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do {
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while (!(dram_addr_mask & j)) {
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j <<= 1;
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}
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*ptbl++ = j;
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j <<= 1;
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i >>= 1;
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} while (i != 0);
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for (i = dram_bank_cnt, j = 0;
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(i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
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unsigned addr = PHYS_SDRAM_1;
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unsigned k;
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unsigned bit;
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for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
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if (bit & j)
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addr |= tbl[k];
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}
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dram_bank_base[j] = addr;
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}
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}
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}
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/* called in board_init_f (before relocation) */
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static unsigned dram_init_banksize_int(int print)
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{
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/*
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* Collect information of banks that has been filled during lowlevel
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* initialization
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*/
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unsigned i;
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unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
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unsigned dram_total = 0;
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unsigned dram_bank_size = *(unsigned *)
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
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unsigned dram_addr_mask = *(unsigned *)
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
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unsigned dram_bank_cnt = *(unsigned *)
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(PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
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dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
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for (i = 0; i < dram_bank_cnt; i++) {
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gd->bd->bi_dram[i].start = dram_bank_base[i];
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gd->bd->bi_dram[i].size = dram_bank_size;
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dram_total += dram_bank_size;
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}
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for (; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = 0;
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gd->bd->bi_dram[i].size = 0;
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}
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if (print) {
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printf("DRAM mask: %08x\n", dram_addr_mask);
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printf("DRAM total %u banks:\n", dram_bank_cnt);
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printf("bank base-address size\n");
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if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
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printf("WARNING! UBoot was configured for %u banks,\n"
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"but %u has been found. "
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"Supressing extra memory banks\n",
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CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
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dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
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}
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for (i = 0; i < dram_bank_cnt; i++) {
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printf(" %u %08x %08x\n",
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i, dram_bank_base[i], dram_bank_size);
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}
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printf(" ------------------------------------------\n"
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"Total %9d\n\n",
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dram_total);
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}
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return dram_total;
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}
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int dram_init_banksize(void)
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{
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dram_init_banksize_int(0);
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return 0;
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}
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/* called in board_init_f (before relocation) */
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int dram_init(void)
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{
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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unsigned sec_id = readl(SECURITY_EXTENSIONID);
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unsigned chip_id = readl(&syscon->chipid);
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printf("CPU: Cirrus Logic ");
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switch (sec_id & 0x000001FE) {
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case 0x00000008:
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printf("EP9301");
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break;
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case 0x00000004:
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printf("EP9307");
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break;
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case 0x00000002:
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printf("EP931x");
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break;
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case 0x00000000:
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printf("EP9315");
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break;
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default:
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printf("<unknown>");
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break;
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}
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printf(" - Rev. ");
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switch (chip_id & 0xF0000000) {
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case 0x00000000:
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printf("A");
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break;
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case 0x10000000:
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printf("B");
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break;
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case 0x20000000:
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printf("C");
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break;
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case 0x30000000:
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printf("D0");
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break;
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case 0x40000000:
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printf("D1");
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break;
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case 0x50000000:
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printf("E0");
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break;
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case 0x60000000:
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printf("E1");
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break;
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case 0x70000000:
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printf("E2");
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break;
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default:
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printf("?");
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break;
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}
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printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
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gd->ram_size = dram_init_banksize_int(1);
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return 0;
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}
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