Lokesh Vutla 4571c519b4 ARM: DRA7: emif: Fix DDR init sequence during warm reset ... Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control) enables Self refresh mode by default and during warm reset the EMIF contents are preserved. After warm reset EMIF sees that it is idle and puts DDR in self-refresh. When in SR, leveling operations cannot be done as DDR can only accept SR exit command, so its hanging during warm reset. In order to fix this reset the power management control register before EMIF initialization if it is a warm reset. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>		2016-03-14 19:18:46 -04:00
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arc	arc: cache - utilize IO coherency (AKA IOC) engine	2016-02-20 11:20:05 +03:00
arm	ARM: DRA7: emif: Fix DDR init sequence during warm reset	2016-03-14 19:18:46 -04:00
avr32	avr32: Use the generic bitops headers	2015-11-05 10:52:31 -05:00
blackfin	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
m68k	m68k: M54418TWR: drop board/freescale/m54418twr/config.mk	2016-01-20 10:19:34 -05:00
microblaze	Kconfig: Move CONFIG_FIT and related options to Kconfig	2016-03-14 19:18:07 -04:00
mips	MIPS: fix mips_cache fallback without __builtin_mips_cache	2016-03-09 11:00:40 +01:00
nds32	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
nios2	nios2: set up the debug UART early	2016-02-06 15:14:25 +08:00
openrisc	openrisc: Fix build errors	2016-01-25 10:40:01 -05:00
powerpc	Kconfig: Move CONFIG_FIT and related options to Kconfig	2016-03-14 19:18:07 -04:00
sandbox	sandbox: Fix building with LLVM	2016-03-08 15:01:46 -05:00
sh	Add more SPDX-License-Identifier tags	2016-01-19 08:31:21 -05:00
sparc	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
x86	x86: Add Intel Cougar Canyon 2 board	2016-02-21 13:42:52 +08:00
.gitignore	.gitignore: drop include/asm/proc from ignore pattern	2014-06-19 11:18:54 -04:00
Kconfig	MIPS: add initial infrastructure for device-tree files	2016-01-16 21:06:45 +01:00