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https://github.com/brain-hackers/u-boot-brain
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026f30ec3e
PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/*
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* Copyright 2014-2015, Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _FSL_LAYERSCAPE_MP_H
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#define _FSL_LAYERSCAPE_MP_H
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/*
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* Each spin table element is defined as
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* struct {
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* uint64_t entry_addr;
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* uint64_t status;
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* uint64_t lpid;
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* uint64_t os_arch;
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* };
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* we pad this struct to 64 bytes so each entry is in its own cacheline
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* the actual spin table is an array of these structures
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*/
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#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
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#define SPIN_TABLE_ELEM_STATUS_IDX 1
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#define SPIN_TABLE_ELEM_LPID_IDX 2
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#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3
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#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
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#define SPIN_TABLE_ELEM_SIZE 64
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#define id_to_core(x) ((x & 3) | (x >> 6))
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#ifndef __ASSEMBLY__
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extern u64 __spin_table[];
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extern u64 __real_cntfrq;
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extern u64 *secondary_boot_code;
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extern size_t __secondary_boot_code_size;
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#ifdef CONFIG_MP
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int fsl_layerscape_wake_seconday_cores(void);
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#else
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static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
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#endif
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void *get_spin_tbl_addr(void);
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phys_addr_t determine_mp_bootpg(void);
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void secondary_boot_func(void);
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int is_core_online(u64 cpu_id);
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u32 cpu_pos_mask(void);
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#endif
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#define IH_ARCH_ARM 2 /* ARM */
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#define IH_ARCH_ARM64 22 /* ARM64 */
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#endif /* _FSL_LAYERSCAPE_MP_H */
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