Gabe Black 452f50f7cf x86: coreboot: Tell u-boot about PCI bus 0 when initializing ... U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>		2012-11-28 11:40:04 -08:00
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coreboot	x86: coreboot: Tell u-boot about PCI bus 0 when initializing	2012-11-28 11:40:04 -08:00
sc520	sc520: fix build warning about unused temp var	2012-03-06 21:05:18 +11:00
config.mk	Convert ISO-8859 files to UTF-8	2011-08-04 23:34:02 +02:00
cpu.c	x86: Put global data on the stack	2012-11-28 11:40:03 -08:00
interrupts.c	x86: Tweak IDT and GDT for alignment and readability	2012-01-04 22:29:40 +11:00
Makefile	x86: Allow excluding reset vector code from u-boot	2012-11-28 11:40:03 -08:00
resetvec.S	Convert ISO-8859 files to UTF-8	2011-08-04 23:34:02 +02:00
start16.S	x86: Tweak IDT and GDT for alignment and readability	2012-01-04 22:29:40 +11:00
start.S	x86: Put global data on the stack	2012-11-28 11:40:03 -08:00
u-boot.lds	x86: Allow excluding reset vector code from u-boot	2012-11-28 11:40:03 -08:00