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https://github.com/brain-hackers/u-boot-brain
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![Bin Meng](/assets/img/avatar_default.png)
At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
247 lines
5.6 KiB
Plaintext
247 lines
5.6 KiB
Plaintext
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-router/intel-irq.h>
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "keyboard.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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/ {
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model = "Intel Crown Bay";
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compatible = "intel,crownbay", "intel,queensbay";
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aliases {
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spi0 = &spi;
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};
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config {
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silent_console = <0>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "cpu-x86";
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reg = <1>;
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intel,apic-id = <1>;
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};
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};
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chosen {
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/*
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* By default the legacy superio serial port is used as the
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* U-Boot serial console. If we want to use UART from Topcliff
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* PCH as the console, change this property to &pciuart#.
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*
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* For example, stdout-path = &pciuart0 will use the first
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* UART on Topcliff PCH.
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*/
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stdout-path = "/serial";
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};
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microcode {
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update@0 {
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#include "microcode/m0220661105_cv.dtsi"
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};
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};
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pci {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-x86";
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pcie@17,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-bridge";
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u-boot,dm-pre-reloc;
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reg = <0x0000b800 0x0 0x0 0x0 0x0>;
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topcliff@0,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "pci-bridge";
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u-boot,dm-pre-reloc;
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reg = <0x00010000 0x0 0x0 0x0 0x0>;
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pciuart0: uart@a,1 {
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compatible = "pci8086,8811.00",
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"pci8086,8811",
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"pciclass,070002",
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"pciclass,0700",
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"ns16550";
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u-boot,dm-pre-reloc;
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reg = <0x00025100 0x0 0x0 0x0 0x0
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0x01025110 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart1: uart@a,2 {
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compatible = "pci8086,8812.00",
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"pci8086,8812",
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"pciclass,070002",
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"pciclass,0700",
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"ns16550";
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u-boot,dm-pre-reloc;
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reg = <0x00025200 0x0 0x0 0x0 0x0
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0x01025210 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart2: uart@a,3 {
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compatible = "pci8086,8813.00",
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"pci8086,8813",
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"pciclass,070002",
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"pciclass,0700",
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"ns16550";
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u-boot,dm-pre-reloc;
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reg = <0x00025300 0x0 0x0 0x0 0x0
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0x01025310 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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pciuart3: uart@a,4 {
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compatible = "pci8086,8814.00",
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"pci8086,8814",
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"pciclass,070002",
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"pciclass,0700",
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"ns16550";
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u-boot,dm-pre-reloc;
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reg = <0x00025400 0x0 0x0 0x0 0x0
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0x01025410 0x0 0x0 0x0 0x0>;
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reg-shift = <0>;
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clock-frequency = <1843200>;
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current-speed = <115200>;
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};
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};
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};
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "intel,pch7";
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#address-cells = <1>;
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#size-cells = <1>;
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irq-router {
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compatible = "intel,queensbay-irq-router";
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intel,pirq-config = "pci";
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intel,pirq-link = <0x60 8>;
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intel,pirq-mask = <0xcee0>;
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intel,pirq-routing = <
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/* TunnelCreek PCI devices */
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PCI_BDF(0, 2, 0) INTA PIRQE
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PCI_BDF(0, 3, 0) INTA PIRQF
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PCI_BDF(0, 23, 0) INTA PIRQA
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PCI_BDF(0, 23, 0) INTB PIRQB
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PCI_BDF(0, 23, 0) INTC PIRQC
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PCI_BDF(0, 23, 0) INTD PIRQD
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PCI_BDF(0, 24, 0) INTA PIRQB
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PCI_BDF(0, 24, 0) INTB PIRQC
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PCI_BDF(0, 24, 0) INTC PIRQD
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PCI_BDF(0, 24, 0) INTD PIRQA
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PCI_BDF(0, 25, 0) INTA PIRQC
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PCI_BDF(0, 25, 0) INTB PIRQD
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PCI_BDF(0, 25, 0) INTC PIRQA
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PCI_BDF(0, 25, 0) INTD PIRQB
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PCI_BDF(0, 26, 0) INTA PIRQD
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PCI_BDF(0, 26, 0) INTB PIRQA
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PCI_BDF(0, 26, 0) INTC PIRQB
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PCI_BDF(0, 26, 0) INTD PIRQC
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PCI_BDF(0, 27, 0) INTA PIRQG
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/*
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* Topcliff PCI devices
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*
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* Note on the Crown Bay board, Topcliff
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* chipset is connected to TunnelCreek
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* PCIe port 0, so its bus number is 1
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* for its PCIe port and 2 for its PCI
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* devices per U-Boot current PCI bus
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* enumeration algorithm.
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*/
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PCI_BDF(1, 0, 0) INTA PIRQA
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PCI_BDF(2, 0, 1) INTA PIRQA
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PCI_BDF(2, 0, 2) INTA PIRQA
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PCI_BDF(2, 2, 0) INTB PIRQD
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PCI_BDF(2, 2, 1) INTB PIRQD
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PCI_BDF(2, 2, 2) INTB PIRQD
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PCI_BDF(2, 2, 3) INTB PIRQD
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PCI_BDF(2, 2, 4) INTB PIRQD
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PCI_BDF(2, 4, 0) INTC PIRQC
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PCI_BDF(2, 4, 1) INTC PIRQC
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PCI_BDF(2, 6, 0) INTD PIRQB
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PCI_BDF(2, 8, 0) INTA PIRQA
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PCI_BDF(2, 8, 1) INTA PIRQA
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PCI_BDF(2, 8, 2) INTA PIRQA
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PCI_BDF(2, 8, 3) INTA PIRQA
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PCI_BDF(2, 10, 0) INTB PIRQD
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PCI_BDF(2, 10, 1) INTB PIRQD
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PCI_BDF(2, 10, 2) INTB PIRQD
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PCI_BDF(2, 10, 3) INTB PIRQD
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PCI_BDF(2, 10, 4) INTB PIRQD
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PCI_BDF(2, 12, 0) INTC PIRQC
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PCI_BDF(2, 12, 1) INTC PIRQC
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PCI_BDF(2, 12, 2) INTC PIRQC
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PCI_BDF(2, 12, 3) INTC PIRQC
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PCI_BDF(2, 12, 4) INTC PIRQC
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>;
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};
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spi: spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich7-spi";
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spi-flash@0 {
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reg = <0>;
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compatible = "sst,25vf016b",
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"spi-flash";
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memory-map = <0xffe00000 0x00200000>;
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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};
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};
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};
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};
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