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![Peter Senna Tschudin](/assets/img/avatar_default.png)
Create board support for GE PPD, based on mx53loco. Use mx53ppd_defconfig make target to configure for this board. Signed-off-by: Peter Senna Tschudin <peter.senna@collabora.com> Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
458 lines
10 KiB
C
458 lines
10 KiB
C
/*
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* Copyright 2017 General Electric Company
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*
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* Based on board/freescale/mx53loco/mx53loco.c:
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*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx53.h>
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#include <asm/arch/clock.h>
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#include <linux/errno.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/mach-imx/mx5_video.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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#include <power/pmic.h>
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#include <dialog_pmic.h>
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#include <fsl_pmic.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <watchdog.h>
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#include "ppd_gpio.h"
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#include <stdlib.h>
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#include "../../ge/common/vpd_reader.h"
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#include <rtc.h>
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#define MX53PPD_LCD_POWER IMX_GPIO_NR(3, 24)
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DECLARE_GLOBAL_DATA_PTR;
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/* Index of I2C1, SEGMENT 1 (see CONFIG_SYS_I2C_BUSES). */
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#define VPD_EEPROM_BUS 2
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/* Address of 24C08 EEPROM. */
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#define VPD_EEPROM_ADDR 0x50
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#define VPD_EEPROM_ADDR_LEN 1
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static u32 mx53_dram_size[2];
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phys_size_t get_effective_memsize(void)
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{
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/*
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* WARNING: We must override get_effective_memsize() function here
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* to report only the size of the first DRAM bank. This is to make
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* U-Boot relocator place U-Boot into valid memory, that is, at the
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* end of the first DRAM bank. If we did not override this function
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* like so, U-Boot would be placed at the address of the first DRAM
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* bank + total DRAM size - sizeof(uboot), which in the setup where
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* each DRAM bank contains 512MiB of DRAM would result in placing
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* U-Boot into invalid memory area close to the end of the first
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* DRAM bank.
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*/
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return mx53_dram_size[0];
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}
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int dram_init(void)
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{
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mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
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mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
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gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = mx53_dram_size[0];
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = mx53_dram_size[1];
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return 0;
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}
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u32 get_board_rev(void)
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{
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return get_cpu_rev() & ~(0xF << 8);
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}
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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#ifdef CONFIG_USB_EHCI_MX5
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int board_ehci_hcd_init(int port)
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{
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/* request VBUS power enable pin, GPIO7_8 */
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imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
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gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
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return 0;
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}
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#endif
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |
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PAD_CTL_ODE),
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NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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PAD_CTL_HYS | PAD_CTL_PKE),
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC3_BASE_ADDR},
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{MMC_SDHC1_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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return 1;
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}
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#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP)
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#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_DSE_HIGH)
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int board_mmc_init(bd_t *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
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SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
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MX53_PAD_EIM_DA11__GPIO3_11,
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};
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static const iomux_v3_cfg_t sd2_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
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MX53_PAD_EIM_DA13__GPIO3_13,
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};
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(sd1_pads,
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ARRAY_SIZE(sd1_pads));
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(sd2_pads,
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ARRAY_SIZE(sd2_pads));
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break;
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default:
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printf("Warning: you configured more ESDHC controller (%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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static void setup_iomux_i2c(void)
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{
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static const iomux_v3_cfg_t i2c1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
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}
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#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
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static struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX53_PAD_EIM_D21__I2C1_SCL | I2C_PAD,
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.gpio_mode = MX53_PAD_EIM_D28__GPIO3_28 | I2C_PAD,
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.gp = IMX_GPIO_NR(3, 28)
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},
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.sda = {
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.i2c_mode = MX53_PAD_EIM_D28__I2C1_SDA | I2C_PAD,
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.gpio_mode = MX53_PAD_EIM_D21__GPIO3_21 | I2C_PAD,
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.gp = IMX_GPIO_NR(3, 21)
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}
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};
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static int clock_1GHz(void)
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{
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int ret;
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u32 ref_clk = MXC_HCLK;
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/*
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* After increasing voltage to 1.25V, we can switch
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* CPU clock to 1GHz and DDR to 400MHz safely
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*/
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ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
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if (ret) {
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printf("CPU: Switch CPU clock to 1GHZ failed\n");
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return -1;
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}
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ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
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ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
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if (ret) {
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printf("CPU: Switch DDR clock to 400MHz failed\n");
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return -1;
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}
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return 0;
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}
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void ppd_gpio_init(void)
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{
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int i;
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imx_iomux_v3_setup_multiple_pads(ppd_pads, ARRAY_SIZE(ppd_pads));
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for (i = 0; i < ARRAY_SIZE(ppd_gpios); ++i)
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gpio_direction_output(ppd_gpios[i].gpio, ppd_gpios[i].value);
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}
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int board_early_init_f(void)
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{
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setup_iomux_fec();
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setup_iomux_lcd();
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ppd_gpio_init();
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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#define VPD_TYPE_INVALID 0x00
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#define VPD_BLOCK_NETWORK 0x20
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#define VPD_BLOCK_HWID 0x44
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#define VPD_PRODUCT_PPD 4
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#define VPD_HAS_MAC1 0x1
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#define VPD_MAC_ADDRESS_LENGTH 6
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struct vpd_cache {
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u8 product_id;
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u8 has;
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unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
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};
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/*
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* Extracts MAC and product information from the VPD.
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*/
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static int vpd_callback(void *userdata, u8 id, u8 version, u8 type, size_t size,
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u8 const *data)
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{
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struct vpd_cache *vpd = (struct vpd_cache *)userdata;
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if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
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size >= 1) {
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vpd->product_id = data[0];
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} else if (id == VPD_BLOCK_NETWORK && version == 1 &&
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type != VPD_TYPE_INVALID) {
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if (size >= 6) {
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vpd->has |= VPD_HAS_MAC1;
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memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
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}
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}
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return 0;
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}
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static void process_vpd(struct vpd_cache *vpd)
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{
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int fec_index = -1;
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if (vpd->product_id == VPD_PRODUCT_PPD)
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fec_index = 0;
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if (fec_index >= 0 && (vpd->has & VPD_HAS_MAC1))
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eth_env_set_enetaddr("ethaddr", vpd->mac1);
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}
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static int read_vpd(uint eeprom_bus)
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{
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struct vpd_cache vpd;
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int res;
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int size = 1024;
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u8 *data;
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unsigned int current_i2c_bus = i2c_get_bus_num();
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res = i2c_set_bus_num(eeprom_bus);
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if (res < 0)
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return res;
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data = malloc(size);
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if (!data)
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return -ENOMEM;
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res = i2c_read(VPD_EEPROM_ADDR, 0, VPD_EEPROM_ADDR_LEN, data, size);
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if (res == 0) {
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memset(&vpd, 0, sizeof(vpd));
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vpd_reader(size, data, &vpd, vpd_callback);
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process_vpd(&vpd);
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}
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free(data);
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i2c_set_bus_num(current_i2c_bus);
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return res;
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}
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static void check_time(void)
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{
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int ret, i;
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struct rtc_time tm;
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u8 retry = 3;
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unsigned int current_i2c_bus = i2c_get_bus_num();
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ret = i2c_set_bus_num(CONFIG_SYS_RTC_BUS_NUM);
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if (ret < 0)
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return;
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rtc_init();
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for (i = 0; i < retry; i++) {
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ret = rtc_get(&tm);
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if (!ret || ret == -EINVAL)
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break;
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}
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if (ret < 0)
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env_set("rtc_status", "RTC_ERROR");
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if (tm.tm_year > 2037) {
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tm.tm_sec = 0;
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tm.tm_min = 0;
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tm.tm_hour = 0;
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tm.tm_mday = 1;
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tm.tm_wday = 2;
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tm.tm_mon = 1;
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tm.tm_year = 2036;
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for (i = 0; i < retry; i++) {
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ret = rtc_set(&tm);
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if (!ret)
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break;
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}
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if (ret < 0)
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env_set("rtc_status", "RTC_ERROR");
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}
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i2c_set_bus_num(current_i2c_bus);
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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mxc_set_sata_internal_clock();
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setup_iomux_i2c();
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setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
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return 0;
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}
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int misc_init_r(void)
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{
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const char *cause;
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/* We care about WDOG only, treating everything else as
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* a power-on-reset.
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*/
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if (get_imx_reset_cause() & 0x0010)
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cause = "WDOG";
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else
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cause = "POR";
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env_set("bootcause", cause);
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return 0;
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}
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int board_late_init(void)
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{
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int res;
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read_vpd(VPD_EEPROM_BUS);
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res = clock_1GHz();
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if (res != 0)
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return res;
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print_cpuinfo();
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hw_watchdog_init();
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check_time();
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: GE PPD\n");
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return 0;
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}
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