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https://github.com/brain-hackers/u-boot-brain
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6a2c1aaae7
-Remove UART address (It is now part of the dts). -Include dummy ns16550 clock -Fix address to last test Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
26 lines
790 B
C
26 lines
790 B
C
/*
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* (C) Copyright 2008
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* Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com
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* This work has been supported by: QTechnology http://qtec.com/
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* based on xparameters-ml507.h by Xilinx
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef XPARAMETER_H
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#define XPARAMETER_H
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#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
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#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
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#define XPAR_INTC_0_BASEADDR 0x81800000
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#define XPAR_SPI_0_BASEADDR 0x83400000
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#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
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#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
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#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
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#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
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#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
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#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
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#endif
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