mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Convert this driver over to use driver model. Since all x86 platforms use it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent code and remove the old x86 spi_init() function. Note that this does not make full use of the new PCI uclass as yet. We still scan the bus looking for the device. It should move to finding its details in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
481 lines
13 KiB
Plaintext
481 lines
13 KiB
Plaintext
menu "x86 architecture"
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depends on X86
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config SYS_ARCH
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default "x86"
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config USE_PRIVATE_LIBGCC
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default y
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choice
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prompt "Target select"
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config TARGET_COREBOOT
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bool "Support coreboot"
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help
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This target is used for running U-Boot on top of Coreboot. In
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this case Coreboot does the early inititalisation, and U-Boot
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takes over once the RAM, video and CPU are fully running.
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U-Boot is loaded as a fallback payload from Coreboot, in
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Coreboot terminology. This method was used for the Chromebook
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Pixel when launched.
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config TARGET_CHROMEBOOK_LINK
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bool "Support Chromebook link"
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help
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This is the Chromebook Pixel released in 2013. It uses an Intel
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i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
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SDRAM. It has a Panther Point platform controller hub, PCIe
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WiFi and Bluetooth. It also includes a 720p webcam, USB SD
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reader, microphone and speakers, display port and 32GB SATA
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solid state drive. There is a Chrome OS EC connected on LPC,
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and it provides a 2560x1700 high resolution touch-enabled LCD
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display.
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config TARGET_CHROMEBOX_PANTHER
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bool "Support Chromebox panther (not available)"
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select n
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help
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Note: At present this must be used with Coreboot. See README.x86
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for instructions.
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This is the Asus Chromebox CN60 released in 2014. It uses an Intel
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Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
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Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
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includes a USB SD reader, four USB3 ports, display port and HDMI
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video output and a 16GB SATA solid state drive. There is no Chrome
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OS EC on this model.
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config TARGET_CROWNBAY
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bool "Support Intel Crown Bay CRB"
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help
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This is the Intel Crown Bay Customer Reference Board. It contains
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the Intel Atom Processor E6xx populated on the COM Express module
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with 1GB DDR2 soldered down memory and a carrier board with the
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Intel Platform Controller Hub EG20T, other system components and
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peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
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config TARGET_MINNOWMAX
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bool "Support Intel Minnowboard MAX"
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help
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This is the Intel Minnowboard MAX. It contains an Atom E3800
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processor in a small form factor with Ethernet, micro-SD, USB 2,
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USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
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It requires some binary blobs - see README.x86 for details.
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Note that PCIE_ECAM_BASE is set up by the FSP so the value used
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by U-Boot matches that value.
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config TARGET_GALILEO
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bool "Support Intel Galileo"
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help
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This is the Intel Galileo board, which is the first in a family of
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Arduino-certified development and prototyping boards based on Intel
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architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
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single-core, single-thread, Intel Pentium processor instrunction set
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architecture (ISA) compatible, operating at speeds up to 400Mhz,
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along with 256MB DDR3 memory. It supports a wide range of industry
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standard I/O interfaces, including a full-sized mini-PCIe slot,
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one 100Mb Ethernet port, a microSD card slot, a USB host port and
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a USB client port.
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endchoice
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config DM
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default y
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config DM_GPIO
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default y
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config DM_SERIAL
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default y
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config DM_SERIAL
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default y
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config DM_SPI
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default y
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config DM_SPI_FLASH
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default y
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config SYS_MALLOC_F_LEN
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default 0x800
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config RAMBASE
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hex
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default 0x100000
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config XIP_ROM_SIZE
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hex
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depends on X86_RESET_VECTOR
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default ROM_SIZE
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config CPU_ADDR_BITS
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int
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default 36
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config HPET_ADDRESS
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hex
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default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
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config SMM_TSEG
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bool
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default n
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config SMM_TSEG_SIZE
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hex
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config X86_RESET_VECTOR
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bool
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default n
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config SYS_X86_START16
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hex
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depends on X86_RESET_VECTOR
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default 0xfffff800
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config BOARD_ROMSIZE_KB_512
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bool
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config BOARD_ROMSIZE_KB_1024
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bool
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config BOARD_ROMSIZE_KB_2048
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bool
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config BOARD_ROMSIZE_KB_4096
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bool
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config BOARD_ROMSIZE_KB_8192
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bool
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config BOARD_ROMSIZE_KB_16384
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bool
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choice
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prompt "ROM chip size"
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depends on X86_RESET_VECTOR
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default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
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default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
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default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
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default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
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default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
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default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
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help
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Select the size of the ROM chip you intend to flash U-Boot on.
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The build system will take care of creating a u-boot.rom file
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of the matching size.
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config UBOOT_ROMSIZE_KB_512
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bool "512 KB"
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help
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Choose this option if you have a 512 KB ROM chip.
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config UBOOT_ROMSIZE_KB_1024
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bool "1024 KB (1 MB)"
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help
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Choose this option if you have a 1024 KB (1 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_2048
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bool "2048 KB (2 MB)"
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help
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Choose this option if you have a 2048 KB (2 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_4096
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bool "4096 KB (4 MB)"
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help
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Choose this option if you have a 4096 KB (4 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_8192
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bool "8192 KB (8 MB)"
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help
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Choose this option if you have a 8192 KB (8 MB) ROM chip.
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config UBOOT_ROMSIZE_KB_16384
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bool "16384 KB (16 MB)"
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help
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Choose this option if you have a 16384 KB (16 MB) ROM chip.
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endchoice
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# Map the config names to an integer (KB).
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config UBOOT_ROMSIZE_KB
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int
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default 512 if UBOOT_ROMSIZE_KB_512
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default 1024 if UBOOT_ROMSIZE_KB_1024
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default 2048 if UBOOT_ROMSIZE_KB_2048
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default 4096 if UBOOT_ROMSIZE_KB_4096
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default 8192 if UBOOT_ROMSIZE_KB_8192
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default 16384 if UBOOT_ROMSIZE_KB_16384
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# Map the config names to a hex value (bytes).
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config ROM_SIZE
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hex
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default 0x80000 if UBOOT_ROMSIZE_KB_512
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default 0x100000 if UBOOT_ROMSIZE_KB_1024
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default 0x200000 if UBOOT_ROMSIZE_KB_2048
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default 0x400000 if UBOOT_ROMSIZE_KB_4096
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default 0x800000 if UBOOT_ROMSIZE_KB_8192
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default 0xc00000 if UBOOT_ROMSIZE_KB_12288
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default 0x1000000 if UBOOT_ROMSIZE_KB_16384
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config HAVE_INTEL_ME
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bool "Platform requires Intel Management Engine"
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help
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Newer higher-end devices have an Intel Management Engine (ME)
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which is a very large binary blob (typically 1.5MB) which is
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required for the platform to work. This enforces a particular
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SPI flash format. You will need to supply the me.bin file in
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your board directory.
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config X86_RAMTEST
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bool "Perform a simple RAM test after SDRAM initialisation"
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help
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If there is something wrong with SDRAM then the platform will
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often crash within U-Boot or the kernel. This option enables a
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very simple RAM test that quickly checks whether the SDRAM seems
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to work correctly. It is not exhaustive but can save time by
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detecting obvious failures.
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config MARK_GRAPHICS_MEM_WRCOMB
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bool "Mark graphics memory as write-combining."
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default n
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help
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The graphics performance may increase if the graphics
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memory is set as write-combining cache type. This option
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enables marking the graphics memory as write-combining.
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menu "Display"
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config FRAMEBUFFER_SET_VESA_MODE
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prompt "Set framebuffer graphics resolution"
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bool
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help
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Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
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choice
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prompt "framebuffer graphics resolution"
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default FRAMEBUFFER_VESA_MODE_117
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depends on FRAMEBUFFER_SET_VESA_MODE
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help
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This option sets the resolution used for the coreboot framebuffer (and
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bootsplash screen).
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config FRAMEBUFFER_VESA_MODE_100
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bool "640x400 256-color"
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config FRAMEBUFFER_VESA_MODE_101
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bool "640x480 256-color"
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config FRAMEBUFFER_VESA_MODE_102
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bool "800x600 16-color"
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config FRAMEBUFFER_VESA_MODE_103
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bool "800x600 256-color"
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config FRAMEBUFFER_VESA_MODE_104
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bool "1024x768 16-color"
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config FRAMEBUFFER_VESA_MODE_105
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bool "1024x7686 256-color"
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config FRAMEBUFFER_VESA_MODE_106
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bool "1280x1024 16-color"
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config FRAMEBUFFER_VESA_MODE_107
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bool "1280x1024 256-color"
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config FRAMEBUFFER_VESA_MODE_108
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bool "80x60 text"
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config FRAMEBUFFER_VESA_MODE_109
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bool "132x25 text"
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config FRAMEBUFFER_VESA_MODE_10A
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bool "132x43 text"
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config FRAMEBUFFER_VESA_MODE_10B
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bool "132x50 text"
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config FRAMEBUFFER_VESA_MODE_10C
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bool "132x60 text"
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config FRAMEBUFFER_VESA_MODE_10D
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bool "320x200 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_10E
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bool "320x200 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_10F
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bool "320x200 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_110
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bool "640x480 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_111
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bool "640x480 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_112
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bool "640x480 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_113
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bool "800x600 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_114
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bool "800x600 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_115
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bool "800x600 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_116
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bool "1024x768 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_117
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bool "1024x768 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_118
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bool "1024x768 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_119
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bool "1280x1024 32k-color (1:5:5:5)"
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config FRAMEBUFFER_VESA_MODE_11A
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bool "1280x1024 64k-color (5:6:5)"
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config FRAMEBUFFER_VESA_MODE_11B
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bool "1280x1024 16.8M-color (8:8:8)"
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config FRAMEBUFFER_VESA_MODE_USER
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bool "Manually select VESA mode"
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endchoice
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# Map the config names to an integer (KB).
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config FRAMEBUFFER_VESA_MODE
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prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
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hex
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default 0x100 if FRAMEBUFFER_VESA_MODE_100
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default 0x101 if FRAMEBUFFER_VESA_MODE_101
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default 0x102 if FRAMEBUFFER_VESA_MODE_102
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default 0x103 if FRAMEBUFFER_VESA_MODE_103
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default 0x104 if FRAMEBUFFER_VESA_MODE_104
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default 0x105 if FRAMEBUFFER_VESA_MODE_105
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default 0x106 if FRAMEBUFFER_VESA_MODE_106
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default 0x107 if FRAMEBUFFER_VESA_MODE_107
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default 0x108 if FRAMEBUFFER_VESA_MODE_108
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default 0x109 if FRAMEBUFFER_VESA_MODE_109
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default 0x10A if FRAMEBUFFER_VESA_MODE_10A
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default 0x10B if FRAMEBUFFER_VESA_MODE_10B
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default 0x10C if FRAMEBUFFER_VESA_MODE_10C
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default 0x10D if FRAMEBUFFER_VESA_MODE_10D
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default 0x10E if FRAMEBUFFER_VESA_MODE_10E
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default 0x10F if FRAMEBUFFER_VESA_MODE_10F
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default 0x110 if FRAMEBUFFER_VESA_MODE_110
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default 0x111 if FRAMEBUFFER_VESA_MODE_111
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default 0x112 if FRAMEBUFFER_VESA_MODE_112
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default 0x113 if FRAMEBUFFER_VESA_MODE_113
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default 0x114 if FRAMEBUFFER_VESA_MODE_114
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default 0x115 if FRAMEBUFFER_VESA_MODE_115
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default 0x116 if FRAMEBUFFER_VESA_MODE_116
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default 0x117 if FRAMEBUFFER_VESA_MODE_117
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default 0x118 if FRAMEBUFFER_VESA_MODE_118
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default 0x119 if FRAMEBUFFER_VESA_MODE_119
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default 0x11A if FRAMEBUFFER_VESA_MODE_11A
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default 0x11B if FRAMEBUFFER_VESA_MODE_11B
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default 0x117 if FRAMEBUFFER_VESA_MODE_USER
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endmenu
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config HAVE_FSP
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bool "Add an Firmware Support Package binary"
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help
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Select this option to add an Firmware Support Package binary to
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the resulting U-Boot image. It is a binary blob which U-Boot uses
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to set up SDRAM and other chipset specific initialization.
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Note: Without this binary U-Boot will not be able to set up its
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SDRAM so will not boot.
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config FSP_FILE
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string "Firmware Support Package binary filename"
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depends on HAVE_FSP
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default "fsp.bin"
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help
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The filename of the file to use as Firmware Support Package binary
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in the board directory.
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config FSP_ADDR
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hex "Firmware Support Package binary location"
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depends on HAVE_FSP
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default 0xfffc0000
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help
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FSP is not Position Independent Code (PIC) and the whole FSP has to
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be rebased if it is placed at a location which is different from the
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perferred base address specified during the FSP build. Use Intel's
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Binary Configuration Tool (BCT) to do the rebase.
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The default base address of 0xfffc0000 indicates that the binary must
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be located at offset 0xc0000 from the beginning of a 1MB flash device.
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config FSP_TEMP_RAM_ADDR
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hex
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default 0x2000000
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help
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Stack top address which is used in FspInit after DRAM is ready and
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CAR is disabled.
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source "arch/x86/cpu/baytrail/Kconfig"
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source "arch/x86/cpu/coreboot/Kconfig"
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source "arch/x86/cpu/ivybridge/Kconfig"
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source "arch/x86/cpu/quark/Kconfig"
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source "arch/x86/cpu/queensbay/Kconfig"
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config TSC_CALIBRATION_BYPASS
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bool "Bypass Time-Stamp Counter (TSC) calibration"
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default n
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help
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By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
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running frequency via Model-Specific Register (MSR) and Programmable
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Interval Timer (PIT). If the calibration does not work on your board,
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select this option and provide a hardcoded TSC running frequency with
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CONFIG_TSC_FREQ_IN_MHZ below.
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Normally this option should be turned on in a simulation environment
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like qemu.
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config TSC_FREQ_IN_MHZ
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int "Time-Stamp Counter (TSC) running frequency in MHz"
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depends on TSC_CALIBRATION_BYPASS
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default 1000
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help
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The running frequency in MHz of Time-Stamp Counter (TSC).
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source "board/coreboot/coreboot/Kconfig"
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source "board/google/chromebook_link/Kconfig"
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source "board/google/chromebox_panther/Kconfig"
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source "board/intel/crownbay/Kconfig"
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source "board/intel/minnowmax/Kconfig"
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source "board/intel/galileo/Kconfig"
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config PCIE_ECAM_BASE
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hex
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default 0xe0000000
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help
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This is the memory-mapped address of PCI configuration space, which
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is only available through the Enhanced Configuration Access
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Mechanism (ECAM) with PCI Express. It can be set up almost
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anywhere. Before it is set up, it is possible to access PCI
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configuration space through I/O access, but memory access is more
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convenient. Using this, PCI can be scanned and configured. This
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should be set to a region that does not conflict with memory
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assigned to PCI devices - i.e. the memory and prefetch regions, as
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passed to pci_set_region().
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endmenu
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