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https://github.com/brain-hackers/u-boot-brain
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430b42f76a
commitc5de2b7eae("arm: socfpga: implement proper peripheral reset") has removed the call to 'reset_deassert_peripherals_handoff()' from socfpga gen5 SPL since the reset driver now handles resets. However, commitc1d4b464c8("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") has re-added this ad-hoc reset code, so that all peripherals were now again enabled instead of letting the drivers enable them by request. While at it, remove this function for gen5 as it should not be used. Fixes: commitc1d4b464c8("ARM: socfpga: Disable bridges in SPL unless booting from FPGA") Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
119 lines
2.7 KiB
C
119 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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/* Assert or de-assert SoCFPGA reset manager reset. */
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void socfpga_per_reset(u32 reset, int set)
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{
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const u32 *reg;
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u32 rstmgr_bank = RSTMGR_BANK(reset);
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switch (rstmgr_bank) {
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case 0:
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reg = &reset_manager_base->mpu_mod_reset;
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break;
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case 1:
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reg = &reset_manager_base->per_mod_reset;
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break;
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case 2:
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reg = &reset_manager_base->per2_mod_reset;
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break;
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case 3:
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reg = &reset_manager_base->brg_mod_reset;
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break;
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case 4:
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reg = &reset_manager_base->misc_mod_reset;
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break;
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default:
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return;
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}
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if (set)
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setbits_le32(reg, 1 << RSTMGR_RESET(reset));
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else
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clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
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}
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/*
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* Assert reset on every peripheral but L4WD0.
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* Watchdog must be kept intact to prevent glitches
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* and/or hangs.
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*/
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void socfpga_per_reset_all(void)
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{
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const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
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writel(~l4wd0, &reset_manager_base->per_mod_reset);
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writel(0xffffffff, &reset_manager_base->per2_mod_reset);
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}
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#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
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#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
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#define L3REGS_REMAP_OCRAM_MASK 0x01
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void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
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{
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u32 brgmask = 0x0;
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u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
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if (h2f)
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brgmask |= BIT(0);
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else
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l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
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if (lwh2f)
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brgmask |= BIT(1);
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else
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l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
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if (f2h)
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brgmask |= BIT(2);
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writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
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writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
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}
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void socfpga_bridges_reset(int enable)
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{
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const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
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L3REGS_REMAP_HPS2FPGA_MASK |
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L3REGS_REMAP_OCRAM_MASK;
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if (enable) {
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/* brdmodrst */
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writel(0x7, &reset_manager_base->brg_mod_reset);
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writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
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} else {
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socfpga_bridges_set_handoff_regs(false, false, false);
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/* Check signal from FPGA. */
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if (!fpgamgr_test_fpga_ready()) {
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/* FPGA not ready, do nothing. We allow system to boot
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* without FPGA ready. So, return 0 instead of error. */
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printf("%s: FPGA not ready, aborting.\n", __func__);
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return;
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}
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/* brdmodrst */
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writel(0, &reset_manager_base->brg_mod_reset);
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/* Remap the bridges into memory map */
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writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
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}
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return;
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}
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