Trent Piepho a5d212a263 mpc8xxx: LCRR[CLKDIV] is sometimes five bits ... On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>		2008-12-19 18:20:25 -06:00
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cache.S	rename CFG_ macros to CONFIG_SYS	2008-10-18 21:54:03 +02:00
config.mk	PPC: Use r2 instead of r29 as global data pointer	2008-02-14 22:43:22 +01:00
cpu_init.c	mpc86xx: Move setup_bats into cpu_init_f	2008-11-10 10:10:02 -06:00
cpu.c	mpc8xxx: LCRR[CLKDIV] is sometimes five bits	2008-12-19 18:20:25 -06:00
ddr-8641.c	rename CFG_ macros to CONFIG_SYS	2008-10-18 21:54:03 +02:00
fdt.c	mpc8[56]xx: Put localbus clock in device tree	2008-12-19 18:20:20 -06:00
interrupts.c	rename CFG_ macros to CONFIG_SYS	2008-10-18 21:54:03 +02:00
Makefile	powerpc: change 86xx SMP boot method	2008-11-04 10:58:50 -06:00
mp.c	powerpc: change 86xx SMP boot method	2008-11-04 10:58:50 -06:00
mp.h	powerpc: change 86xx SMP boot method	2008-11-04 10:58:50 -06:00
release.S	Fix new found CFG_	2008-12-14 10:55:30 +01:00
speed.c	rename CFG_ macros to CONFIG_SYS	2008-10-18 21:54:03 +02:00
start.S	Coding style cleanup, update CHANGELOG.	2008-12-16 01:02:17 +01:00
traps.c	Fix some more print() format errors.	2008-07-11 01:16:00 +02:00