mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-05 01:33:44 +09:00
44453b25b0
Rework the HMATRIX configuration interface so that it becomes easier to configure the HMATRIX for boards with special needs, and add new parts. The HMATRIX header file has been split into a general, chip-independent part with register definitions, etc. and a chip-specific part with SFR bitfield definitions and master/slave identifiers. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
96 lines
2.1 KiB
C
96 lines
2.1 KiB
C
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hmatrix.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_ATSTK1006
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/* Dual MT48LC16M16A2-7E on daughterboard */
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static const struct sdram_info sdram = {
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.phys_addr = CFG_SDRAM_BASE,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 2,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 4,
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.txsr = 7,
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/* 7.81 us */
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.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
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};
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#else
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/* MT48LC2M32B2-5 on motherboard */
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static const struct sdram_info sdram = {
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.phys_addr = CFG_SDRAM_BASE,
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.row_bits = 11,
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.col_bits = 8,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 5,
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.txsr = 5,
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/* 15.6 us */
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.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
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};
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#endif
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
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gpio_enable_ebi();
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gpio_enable_usart1();
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#if defined(CONFIG_MACB)
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gpio_enable_macb0();
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gpio_enable_macb1();
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#endif
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#if defined(CONFIG_MMC)
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gpio_enable_mmci();
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#endif
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return 0;
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}
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long int initdram(int board_type)
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{
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return sdram_init(&sdram);
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}
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void board_init_info(void)
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{
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gd->bd->bi_phy_id[0] = 0x10;
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gd->bd->bi_phy_id[1] = 0x11;
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}
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