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![Jean-Jacques Hiblot](/assets/img/avatar_default.png)
The xhci.h header file is currently located under drivers/usb/xhci Move it to the include/usb folder to make it available to drivers that are not under drivers/usb/xhci Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
216 lines
5.2 KiB
C
216 lines
5.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015,2016 Freescale Semiconductor, Inc.
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*
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* FSL USB HOST xHCI Controller
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*
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
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*/
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#include <common.h>
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#include <usb.h>
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#include <linux/errno.h>
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#include <linux/compat.h>
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#include <linux/usb/xhci-fsl.h>
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#include <linux/usb/dwc3.h>
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#include <usb/xhci.h>
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#include <fsl_errata.h>
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#include <fsl_usb.h>
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#include <dm.h>
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/* Declare global data pointer */
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#if !CONFIG_IS_ENABLED(DM_USB)
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static struct fsl_xhci fsl_xhci;
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unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
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#else
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struct xhci_fsl_priv {
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struct xhci_ctrl xhci;
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fdt_addr_t hcd_base;
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struct fsl_xhci ctx;
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};
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#endif
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__weak int __board_usb_init(int index, enum usb_init_type init)
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{
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return 0;
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}
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static int erratum_a008751(void)
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{
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#if defined(CONFIG_TARGET_LS2080AQDS) || defined(CONFIG_TARGET_LS2080ARDB) ||\
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defined(CONFIG_TARGET_LS2080AQDS)
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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writel(SCFG_USB3PRM1CR_INIT, scfg + SCFG_USB3PRM1CR / 4);
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return 0;
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#endif
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return 1;
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}
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static void fsl_apply_xhci_errata(void)
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{
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int ret;
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if (has_erratum_a008751()) {
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ret = erratum_a008751();
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if (ret != 0)
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puts("Failed to apply erratum a008751\n");
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}
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}
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static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg)
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{
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clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,
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USB3_ENABLE_BEAT_BURST);
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setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);
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}
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static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
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{
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int ret = 0;
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ret = dwc3_core_init(fsl_xhci->dwc3_reg);
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if (ret) {
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debug("%s:failed to initialize core\n", __func__);
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return ret;
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}
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/* We are hard-coding DWC3 core to Host Mode */
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dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
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/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
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dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
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/* Change beat burst and outstanding pipelined transfers requests */
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fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);
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/*
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* A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not
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* reliably support Rx Detect in P3 mode(P3 is the default
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* setting). Therefore, some USB3.0 devices may not be detected
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* reliably in Super Speed mode. So, USB controller to configure
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* USB in P2 mode whenever the Receive Detect feature is required.
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* whenever the Receive Detect feature is required.
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*/
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if (has_erratum_a010151())
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clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],
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DWC3_GUSB3PIPECTL_DISRXDETP3,
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DWC3_GUSB3PIPECTL_DISRXDETP3);
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return ret;
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}
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static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
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{
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/*
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* Currently fsl socs do not support PHY shutdown from
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* sw. But this support may be added in future socs.
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*/
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return 0;
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}
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#if CONFIG_IS_ENABLED(DM_USB)
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static int xhci_fsl_probe(struct udevice *dev)
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{
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struct xhci_fsl_priv *priv = dev_get_priv(dev);
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struct xhci_hccr *hccr;
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struct xhci_hcor *hcor;
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int ret = 0;
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/*
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* Get the base address for XHCI controller from the device node
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*/
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priv->hcd_base = devfdt_get_addr(dev);
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if (priv->hcd_base == FDT_ADDR_T_NONE) {
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debug("Can't get the XHCI register base address\n");
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return -ENXIO;
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}
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priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;
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priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +
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DWC3_REG_OFFSET);
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fsl_apply_xhci_errata();
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ret = fsl_xhci_core_init(&priv->ctx);
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if (ret < 0) {
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puts("Failed to initialize xhci\n");
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return ret;
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}
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hccr = (struct xhci_hccr *)(priv->ctx.hcd);
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hcor = (struct xhci_hcor *)((uintptr_t) hccr
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+ HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
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debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",
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(uintptr_t)hccr, (uintptr_t)hcor,
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(uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));
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return xhci_register(dev, hccr, hcor);
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}
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static int xhci_fsl_remove(struct udevice *dev)
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{
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struct xhci_fsl_priv *priv = dev_get_priv(dev);
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fsl_xhci_core_exit(&priv->ctx);
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return xhci_deregister(dev);
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}
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static const struct udevice_id xhci_usb_ids[] = {
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{ .compatible = "fsl,layerscape-dwc3", },
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{ }
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};
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U_BOOT_DRIVER(xhci_fsl) = {
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.name = "xhci_fsl",
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.id = UCLASS_USB,
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.of_match = xhci_usb_ids,
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.probe = xhci_fsl_probe,
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.remove = xhci_fsl_remove,
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.ops = &xhci_usb_ops,
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.platdata_auto_alloc_size = sizeof(struct usb_platdata),
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.priv_auto_alloc_size = sizeof(struct xhci_fsl_priv),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#else
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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struct fsl_xhci *ctx = &fsl_xhci;
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int ret = 0;
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ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
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ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
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ret = board_usb_init(index, USB_INIT_HOST);
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if (ret != 0) {
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puts("Failed to initialize board for USB\n");
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return ret;
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}
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fsl_apply_xhci_errata();
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ret = fsl_xhci_core_init(ctx);
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if (ret < 0) {
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puts("Failed to initialize xhci\n");
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return ret;
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}
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*hccr = (struct xhci_hccr *)ctx->hcd;
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*hcor = (struct xhci_hcor *)((uintptr_t) *hccr
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+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
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(uintptr_t)*hccr, (uintptr_t)*hcor,
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(uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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return ret;
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}
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void xhci_hcd_stop(int index)
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{
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struct fsl_xhci *ctx = &fsl_xhci;
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fsl_xhci_core_exit(ctx);
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}
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#endif
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