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![]() The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> |
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cpld.c | ||
cpld.h | ||
ddr.c | ||
ddr.h | ||
eth.c | ||
Kconfig | ||
ls1043ardb_pbi.cfg | ||
ls1043ardb_rcw_nand.cfg | ||
ls1043ardb_rcw_sd.cfg | ||
ls1043ardb.c | ||
MAINTAINERS | ||
Makefile | ||
README |
Overview -------- The LS1043A Reference Design Board (RDB) is a high-performance computing, evaluation, and development platform that supports the QorIQ LS1043A LayerScape Architecture processor. The LS1043ARDB provides SW development platform for the Freescale LS1043A processor series, with a complete debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A SoC overview. LS1043ARDB board Overview ----------------------- - SERDES Connections, 4 lanes supporting: - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and standard PCIe card - QSGMII with x4 RJ45 connector - XFI with x1 RJ45 connector - DDR Controller - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus - One 128MB NOR flash 16-bit data bus - One 512 MB NAND flash with ECC support - CPLD connection - USB 3.0 - Two super speed USB 3.0 Type A ports - SDHC: connects directly to a full SD/MMC slot - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - 4 I2C controllers - UART - Two 4-pin serial ports at up to 115.2 Kbit/s - Two DB9 D-Type connectors supporting one Serial port each - ARM JTAG support Memory map from core's view ---------------------------- Start Address End Address Description Size 0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB 0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB 0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB 0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB Booting Options --------------- a) NOR boot b) NAND boot c) SD boot