mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-17 10:13:21 +09:00
aa72e43bb7
Some functions were internal to the apbh dma driver, so annotate them static. Some of the functions weren't used at all so drop them. This makes the U-Boot binary smaller by about 1500 bytes. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
146 lines
4.0 KiB
C
146 lines
4.0 KiB
C
/*
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* Freescale i.MX28 APBH DMA
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __DMA_H__
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#define __DMA_H__
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#include <linux/list.h>
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#ifndef CONFIG_ARCH_DMA_PIO_WORDS
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#define DMA_PIO_WORDS 15
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#else
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#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
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#endif
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#define MXS_DMA_ALIGNMENT 32
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/*
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* MXS DMA channels
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*/
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enum {
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MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
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MXS_DMA_CHANNEL_AHB_APBH_SSP1,
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MXS_DMA_CHANNEL_AHB_APBH_SSP2,
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MXS_DMA_CHANNEL_AHB_APBH_SSP3,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
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MXS_DMA_CHANNEL_AHB_APBH_SSP,
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MXS_MAX_DMA_CHANNELS,
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};
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/*
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* MXS DMA hardware command.
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*
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* This structure describes the in-memory layout of an entire DMA command,
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* including space for the maximum number of PIO accesses. See the appropriate
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* reference manual for a detailed description of what these fields mean to the
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* DMA hardware.
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*/
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#define MXS_DMA_DESC_COMMAND_MASK 0x3
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#define MXS_DMA_DESC_COMMAND_OFFSET 0
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#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0
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#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1
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#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2
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#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3
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#define MXS_DMA_DESC_CHAIN (1 << 2)
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#define MXS_DMA_DESC_IRQ (1 << 3)
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#define MXS_DMA_DESC_NAND_LOCK (1 << 4)
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#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5)
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#define MXS_DMA_DESC_DEC_SEM (1 << 6)
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#define MXS_DMA_DESC_WAIT4END (1 << 7)
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#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8)
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#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9)
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#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12)
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#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12
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#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16)
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#define MXS_DMA_DESC_BYTES_OFFSET 16
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struct mxs_dma_cmd {
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unsigned long next;
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unsigned long data;
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union {
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dma_addr_t address;
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unsigned long alternate;
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};
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unsigned long pio_words[DMA_PIO_WORDS];
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};
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/*
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* MXS DMA command descriptor.
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*
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* This structure incorporates an MXS DMA hardware command structure, along
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* with metadata.
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*/
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#define MXS_DMA_DESC_FIRST (1 << 0)
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#define MXS_DMA_DESC_LAST (1 << 1)
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#define MXS_DMA_DESC_READY (1 << 31)
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struct mxs_dma_desc {
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struct mxs_dma_cmd cmd;
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unsigned int flags;
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dma_addr_t address;
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void *buffer;
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struct list_head node;
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};
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/**
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* MXS DMA channel
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*
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* This structure represents a single DMA channel. The MXS platform code
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* maintains an array of these structures to represent every DMA channel in the
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* system (see mxs_dma_channels).
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*/
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#define MXS_DMA_FLAGS_IDLE 0
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#define MXS_DMA_FLAGS_BUSY (1 << 0)
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#define MXS_DMA_FLAGS_FREE 0
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#define MXS_DMA_FLAGS_ALLOCATED (1 << 16)
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#define MXS_DMA_FLAGS_VALID (1 << 31)
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struct mxs_dma_chan {
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const char *name;
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unsigned long dev;
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struct mxs_dma_device *dma;
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unsigned int flags;
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unsigned int active_num;
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unsigned int pending_num;
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struct list_head active;
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struct list_head done;
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};
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struct mxs_dma_desc *mxs_dma_desc_alloc(void);
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void mxs_dma_desc_free(struct mxs_dma_desc *);
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int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc);
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int mxs_dma_go(int chan);
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int mxs_dma_init(void);
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#endif /* __DMA_H__ */
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