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![Stefan Roese](/assets/img/avatar_default.png)
Additionally the SDRAM address decoding register address is not hard coded in the C code any more. A define is introduced for this base address. This makes is possible to use those gpio functions from other MVEBU SoC's as well. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Luka Perkov <luka@openwrt.org> Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
69 lines
1.5 KiB
C
69 lines
1.5 KiB
C
/*
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* Copyright (C) 2011-2012
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* Gerald Kerma <dreagle@doukki.net>
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* Luka Perkov <luka@openwrt.org>
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* Simon Baatz <gmbnomis@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/arch/mpp.h>
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#include "ib62x0.h"
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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/*
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* default gpio configuration
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* There are maximum 64 gpios controlled through 2 sets of registers
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* the below configuration configures mainly initial LED status
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*/
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mvebu_config_gpio(IB62x0_OE_VAL_LOW,
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IB62x0_OE_VAL_HIGH,
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IB62x0_OE_LOW, IB62x0_OE_HIGH);
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/* Set SATA activity LEDs to default off */
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writel(MVSATAHC_LED_POLARITY_CTRL, MVSATAHC_LED_CONF_REG);
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/* Multi-Purpose Pins Functionality configuration */
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static const u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_SATA1_ACTn,
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MPP21_SATA0_ACTn,
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MPP22_GPIO, /* Power LED red */
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MPP24_GPIO, /* Power off device */
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MPP25_GPIO, /* Power LED green */
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MPP27_GPIO, /* USB transfer LED */
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MPP28_GPIO, /* Reset button */
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MPP29_GPIO, /* USB Copy button */
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0
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};
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kirkwood_mpp_conf(kwmpp_config, NULL);
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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return 0;
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}
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