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https://github.com/brain-hackers/u-boot-brain
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30de1ba0d3
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Add support for detection J7200 SoC Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
23 lines
634 B
C
23 lines
634 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Andreas Dannenberg <dannenberg@ti.com>
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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void sdelay(unsigned long loops);
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u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
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u32 bound);
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struct ti_sci_handle *get_ti_sci_handle(void);
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int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
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int do_board_detect(void);
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void release_resources_for_core_shutdown(void);
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int fdt_disable_node(void *blob, char *node_path);
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bool soc_is_j721e(void);
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bool soc_is_j7200(void);
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#endif
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