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https://github.com/brain-hackers/u-boot-brain
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9cf7f46307
Add new Microchip sam9x60 SoC based on an ARM926. Signed-off-by: Sandeep Sheriker Mallikarjun <sandeepsheriker.mallikarjun@microchip.com> [tudor.ambarus@microchip.com: fix SFR definition] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
170 lines
5.2 KiB
C
170 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Chip-specific header file for the SAM9X60 SoC.
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*
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* Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
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*/
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#ifndef __SAM9X60_H__
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#define __SAM9X60_H__
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller */
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#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
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#define ATMEL_ID_PIOA 2 /* Parallel I/O Controller A */
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#define ATMEL_ID_PIOB 3 /* Parallel I/O Controller B */
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#define ATMEL_ID_PIOC 4 /* Parallel I/O Controller C */
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#define ATMEL_ID_FLEXCOM0 5 /* FLEXCOM 0 */
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#define ATMEL_ID_FLEXCOM1 6 /* FLEXCOM 1 */
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#define ATMEL_ID_FLEXCOM2 7 /* FLEXCOM 2 */
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#define ATMEL_ID_FLEXCOM3 8 /* FLEXCOM 3 */
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#define ATMEL_ID_FLEXCOM6 9 /* FLEXCOM 6 */
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#define ATMEL_ID_FLEXCOM7 10 /* FLEXCOM 7 */
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#define ATMEL_ID_FLEXCOM8 11 /* FLEXCOM 8 */
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#define ATMEL_ID_SDMMC0 12 /* SDMMC 0 */
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#define ATMEL_ID_FLEXCOM4 13 /* FLEXCOM 4 */
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#define ATMEL_ID_FLEXCOM5 14 /* FLEXCOM 5 */
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#define ATMEL_ID_FLEXCOM9 15 /* FLEXCOM 9 */
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#define ATMEL_ID_FLEXCOM10 16 /* FLEXCOM 10 */
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#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
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#define ATMEL_ID_ADC 19 /* ADC Controller */
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#define ATMEL_ID_XDMAC0 20 /* XDMA Controller 0 */
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#define ATMEL_ID_MATRIX 21 /* BUS Matrix */
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#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
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#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
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#define ATMEL_ID_EMAC0 24 /* Ethernet MAC 0 */
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#define ATMEL_ID_LCDC 25 /* LCD Controller */
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#define ATMEL_ID_SDMMC1 26 /* SDMMC 1 */
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#define ATMEL_ID_EMAC1 27 /* Ethernet MAC `1 */
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#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
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#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
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#define ATMEL_ID_TRNG 38 /* True Random Number Generator */
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#define ATMEL_ID_PIOD 44 /* Parallel I/O Controller D */
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#define ATMEL_ID_DBGU 47 /* Debug unit */
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/*
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* User Peripheral physical base addresses.
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*/
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#define ATMEL_BASE_FLEXCOM4 0xf0000000
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#define ATMEL_BASE_FLEXCOM5 0xf0004000
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#define ATMEL_BASE_XDMA0 0xf0008000
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#define ATMEL_BASE_SSC 0xf0010000
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#define ATMEL_BASE_QSPI 0xf0014000
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#define ATMEL_BASE_CAN0 0xf8000000
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#define ATMEL_BASE_CAN1 0xf8004000
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#define ATMEL_BASE_TC0 0xf8008000
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#define ATMEL_BASE_TC1 0xf8008040
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#define ATMEL_BASE_TC2 0xf8008080
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#define ATMEL_BASE_TC3 0xf800c000
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#define ATMEL_BASE_TC4 0xf800c040
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#define ATMEL_BASE_TC5 0xf800c080
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#define ATMEL_BASE_FLEXCOM6 0xf8010000
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#define ATMEL_BASE_FLEXCOM7 0xf8014000
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#define ATMEL_BASE_FLEXCOM8 0xf8018000
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#define ATMEL_BASE_FLEXCOM0 0xf801c000
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#define ATMEL_BASE_FLEXCOM1 0xf8020000
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#define ATMEL_BASE_FLEXCOM2 0xf8024000
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#define ATMEL_BASE_FLEXCOM3 0xf8028000
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#define ATMEL_BASE_EMAC0 0xf802c000
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#define ATMEL_BASE_EMAC1 0xf8030000
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#define ATMEL_BASE_PWM 0xf8034000
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#define ATMEL_BASE_LCDC 0xf8038000
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#define ATMEL_BASE_UDPHS 0xf803c000
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#define ATMEL_BASE_FLEXCOM9 0xf8040000
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#define ATMEL_BASE_FLEXCOM10 0xf8044000
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#define ATMEL_BASE_ISI 0xf8048000
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#define ATMEL_BASE_ADC 0xf804c000
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#define ATMEL_BASE_SFR 0xf8050000
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#define ATMEL_BASE_SYS 0xffffc000
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/*
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* System Peripherals
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*/
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#define ATMEL_BASE_MATRIX 0xffffde00
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#define ATMEL_BASE_PMECC 0xffffe000
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#define ATMEL_BASE_PMERRLOC 0xffffe600
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#define ATMEL_BASE_MPDDRC 0xffffe800
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#define ATMEL_BASE_SMC 0xffffea00
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#define ATMEL_BASE_SDRAMC 0xffffec00
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#define ATMEL_BASE_AIC 0xfffff100
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#define ATMEL_BASE_DBGU 0xfffff200
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#define ATMEL_BASE_PIOA 0xfffff400
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#define ATMEL_BASE_PIOB 0xfffff600
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#define ATMEL_BASE_PIOC 0xfffff800
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#define ATMEL_BASE_PIOD 0xfffffa00
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#define ATMEL_BASE_PMC 0xfffffc00
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#define ATMEL_BASE_RSTC 0xfffffe00
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#define ATMEL_BASE_SHDWC 0xfffffe10
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#define ATMEL_BASE_PIT 0xfffffe40
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#define ATMEL_BASE_GPBR 0xfffffe60
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#define ATMEL_BASE_RTC 0xfffffea8
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#define ATMEL_BASE_WDT 0xffffff80
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/*
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* Internal Memory.
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*/
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#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
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#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
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#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
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#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
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#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
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/*
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* External memory
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*/
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#define ATMEL_BASE_CS0 0x10000000
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#define ATMEL_BASE_CS1 0x20000000
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#define ATMEL_BASE_CS2 0x30000000
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#define ATMEL_BASE_CS3 0x40000000
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#define ATMEL_BASE_CS4 0x50000000
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#define ATMEL_BASE_CS5 0x60000000
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#define ATMEL_BASE_SDMMC0 0x80000000
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#define ATMEL_BASE_SDMMC1 0x90000000
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/* 9x60 series chip id definitions */
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#define ARCH_ID_SAM9X60 0x819b35a0
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#define ARCH_ID_VERSION_MASK 0x1f
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#define ARCH_EXID_SAM9X60 0x00000000
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#define cpu_is_sam9x60() (get_chip_id() == ARCH_ID_SAM9X60)
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/*
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* Cpu Name
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*/
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#define ATMEL_CPU_NAME get_cpu_name()
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/* Timer */
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#define CONFIG_SYS_TIMER_COUNTER 0xfffffe4c
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/*
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* Other misc defines
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*/
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#define ATMEL_PIO_PORTS 4
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#define CPU_HAS_PCR
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#define CPU_NO_PLLB
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#define PLL_ID_PLLA 0
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#define PLL_ID_UPLL 1
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/*
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* PMECC table in ROM
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*/
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#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
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#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000
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/*
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* SAM9X60 specific prototypes
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*/
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#ifndef __ASSEMBLY__
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unsigned int get_chip_id(void);
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unsigned int get_extension_chip_id(void);
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unsigned int has_emac1(void);
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unsigned int has_emac0(void);
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unsigned int has_lcdc(void);
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char *get_cpu_name(void);
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#endif
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#endif
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