mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 12:46:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
127 lines
2.5 KiB
ArmAsm
127 lines
2.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* armboot - Startup Code for SA1100 CPU
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*
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* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
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* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
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* Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
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* Copyright (c) 2001 Alex Züpke <azu@sysgo.de>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* relocate armboot to ram
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* setup stack
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* jump to second stage
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*
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*************************************************************************
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*/
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.globl reset
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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mov pc, lr
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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/* Interrupt-Controller base address */
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IC_BASE: .word 0x90050000
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#define ICMR 0x04
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/* Reset-Controller */
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RST_BASE: .word 0x90030000
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#define RSRR 0x00
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#define RCSR 0x04
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/* PWR */
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PWR_BASE: .word 0x90020000
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#define PSPR 0x08
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#define PPCR 0x14
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cpuspeed: .word CONFIG_SYS_CPUSPEED
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cpu_init_crit:
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/*
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* mask all IRQs
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*/
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ldr r0, IC_BASE
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mov r1, #0x00
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str r1, [r0, #ICMR]
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/* set clock speed */
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ldr r0, PWR_BASE
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ldr r1, cpuspeed
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str r1, [r0, #PPCR]
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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/*
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* before relocating, we have to setup RAM timing
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* because memory timing is board-dependend, you will
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* find a lowlevel_init.S in your board directory.
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*/
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mov ip, lr
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bl lowlevel_init
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mov lr, ip
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#endif
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/*
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* disable MMU stuff and enable I-cache
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*/
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mrc p15,0,r0,c1,c0
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bic r0, r0, #0x00002000 @ clear bit 13 (X)
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bic r0, r0, #0x0000000f @ clear bits 3-0 (WCAM)
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orr r0, r0, #0x00001000 @ set bit 12 (I) Icache
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orr r0, r0, #0x00000002 @ set bit 1 (A) Align
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mcr p15,0,r0,c1,c0
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/*
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* flush v4 I/D caches
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
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mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
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mov pc, lr
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