mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 03:49:43 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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*
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* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
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*
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* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*/
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#include <common.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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void mx31_uart1_hw_init(void)
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{
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/* setup pins for UART1 */
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mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
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mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
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mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
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mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
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}
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void mx31_uart2_hw_init(void)
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{
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/* setup pins for UART2 */
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mx31_gpio_mux(MUX_RXD2__UART2_RXD_MUX);
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mx31_gpio_mux(MUX_TXD2__UART2_TXD_MUX);
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mx31_gpio_mux(MUX_RTS2__UART2_RTS_B);
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mx31_gpio_mux(MUX_CTS2__UART2_CTS_B);
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}
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#ifdef CONFIG_MXC_SPI
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/*
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* Note: putting several spi setups here makes no sense as they may differ
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* at board level (physical pin SS0 of CSPI2 may aswell be used as SS0 of CSPI3)
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*/
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void mx31_spi2_hw_init(void)
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{
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/* SPI2 */
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mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
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mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
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mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
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mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
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mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
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mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
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mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
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/* start SPI2 clock */
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__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
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}
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#endif
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