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https://github.com/brain-hackers/u-boot-brain
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6cadaa046b
For the peripheral clock, provide the clock ops for the clock provider, such as spi0_clk. The .of_xlate is to get the clk->id, the .enable is to enable the spi0 peripheral clock, the .get_rate is to get the clock frequency. The driver for periph32ck node is responsible for recursively binding its children as clk devices, not provide the clock ops. So do the generated clock and system clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
91 lines
1.9 KiB
C
91 lines
1.9 KiB
C
/*
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* Copyright (C) 2016 Atmel Corporation
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* Wenyou.Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <linux/io.h>
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#include <mach/at91_pmc.h>
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#include "pmc.h"
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#define PERIPHERAL_ID_MIN 2
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#define PERIPHERAL_ID_MAX 31
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#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
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/**
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* sam9x5_periph_clk_bind() - for the periph clock driver
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* Recursively bind its children as clk devices.
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*
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* @return: 0 on success, or negative error code on failure
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*/
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static int sam9x5_periph_clk_bind(struct udevice *dev)
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{
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return at91_clk_sub_device_bind(dev, "periph-clk");
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}
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static const struct udevice_id sam9x5_periph_clk_match[] = {
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{ .compatible = "atmel,at91sam9x5-clk-peripheral" },
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{}
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};
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U_BOOT_DRIVER(sam9x5_periph_clk) = {
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.name = "sam9x5-periph-clk",
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.id = UCLASS_MISC,
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.of_match = sam9x5_periph_clk_match,
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.bind = sam9x5_periph_clk_bind,
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};
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/*---------------------------------------------------------*/
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static int periph_clk_enable(struct clk *clk)
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{
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struct pmc_platdata *plat = dev_get_platdata(clk->dev);
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struct at91_pmc *pmc = plat->reg_base;
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if (clk->id < PERIPHERAL_ID_MIN)
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return -1;
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writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
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setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN);
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return 0;
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}
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static ulong periph_get_rate(struct clk *clk)
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{
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struct udevice *dev;
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struct clk clk_dev;
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ulong clk_rate;
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int ret;
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dev = dev_get_parent(clk->dev);
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ret = clk_get_by_index(dev, 0, &clk_dev);
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if (ret)
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return ret;
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clk_rate = clk_get_rate(&clk_dev);
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clk_free(&clk_dev);
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return clk_rate;
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}
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static struct clk_ops periph_clk_ops = {
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.of_xlate = at91_clk_of_xlate,
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.enable = periph_clk_enable,
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.get_rate = periph_get_rate,
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};
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U_BOOT_DRIVER(clk_periph) = {
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.name = "periph-clk",
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.id = UCLASS_CLK,
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.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
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.probe = at91_clk_probe,
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.ops = &periph_clk_ops,
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};
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