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https://github.com/brain-hackers/u-boot-brain
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64134f0112
With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
92 lines
2.6 KiB
Plaintext
92 lines
2.6 KiB
Plaintext
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x387c0000; /* Where bootcode in the flash is mapped */
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.text : { *(.text); }
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. = ALIGN(4);
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.rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
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. = 0x400000; /* Ram data segment to use */
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_i386boot_romdata_dest = ABSOLUTE(.);
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.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
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_i386boot_romdata_start = LOADADDR(.data);
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. = ALIGN(4);
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.got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
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_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got);
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. = ALIGN(4);
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_i386boot_bss_start = ABSOLUTE(.);
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.bss (NOLOAD) : { *(.bss) }
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_i386boot_bss_size = SIZEOF(.bss);
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/* 16bit realmode trampoline code */
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.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) }
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_i386boot_realmode = LOADADDR(.realmode);
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_i386boot_realmode_size = SIZEOF(.realmode);
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/* 16bit BIOS emulation code (just enough to boot Linux) */
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.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
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_i386boot_bios = LOADADDR(.bios);
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_i386boot_bios_size = SIZEOF(.bios);
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. = .;
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__u_boot_cmd_start = .;
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.u_boot_cmd : { *(.u_boot_cmd) }
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__u_boot_cmd_end = .;
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/* The load addresses below assumes that the flash
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* will be mapped so that 0x387f0000 == 0xffff0000
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* at reset time
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*
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* The fe00 and ff00 offsets of the start32 and start16
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* segments are arbitrary, the just have to be mapped
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* at reset and the code have to fit.
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* The fff0 offset of reset is important, however.
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*/
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. = 0xfffffe00;
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.start32 : AT (0x387ffe00) { *(.start32); }
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. = 0xff00;
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.start16 : AT (0x387fff00) { *(.start16); }
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. = 0xfff0;
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.reset : AT (0x387ffff0) { *(.reset); }
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_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
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}
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