mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
2a4741d9a1
The pxa255_idp being an old unmaintained board showed several issues: 1. CONFIG_INIT_CRITICAL was still defined. 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. 3. Symbol flash_addr was undeclared. 4. The boards lowlevel_init function was still called memsetup. 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. 6. Using -march=armv5 instead of -march=armv5te resulted in lots of 'target CPU does not support interworking' warnings on recent compilers. 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as indexes rather than the register definitions from the pxa-regs header file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to avoid any ambiguities. 8. There were several redefinition warnings concerning ICMR, OSMR3, OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. 9. The board configuration file was rather outdated. 10. The part header file defined the vendor, product and revision arrays as unsigned chars instead of just chars in the block_dev_desc_t structure. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
497 lines
14 KiB
ArmAsm
497 lines
14 KiB
ArmAsm
/*
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* Most of this taken from Redboot hal_platform_setup.h with cleanup
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*
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* NOTE: I haven't clean this up considerably, just enough to get it
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* running. See hal_platform_setup.h for the source. See
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* board/cradle/lowlevel_init.S for another PXA250 setup that is
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* much cleaner.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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DRAM_SIZE: .long CFG_DRAM_SIZE
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/* wait for coprocessor write complete */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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/*
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* Memory setup
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*/
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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#ifdef DEBUG_BLINK_ENABLE
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/* 3rd blink */
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bl blink
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#endif
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/* Set up GPIO pins first ----------------------------------------- */
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ldr r0, =GPSR0
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ldr r1, =CFG_GPSR0_VAL
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str r1, [r0]
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ldr r0, =GPSR1
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ldr r1, =CFG_GPSR1_VAL
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str r1, [r0]
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ldr r0, =GPSR2
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ldr r1, =CFG_GPSR2_VAL
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str r1, [r0]
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ldr r0, =GPCR0
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ldr r1, =CFG_GPCR0_VAL
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str r1, [r0]
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ldr r0, =GPCR1
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ldr r1, =CFG_GPCR1_VAL
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str r1, [r0]
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ldr r0, =GPCR2
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ldr r1, =CFG_GPCR2_VAL
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str r1, [r0]
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ldr r0, =GPDR0
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ldr r1, =CFG_GPDR0_VAL
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str r1, [r0]
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ldr r0, =GPDR1
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ldr r1, =CFG_GPDR1_VAL
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str r1, [r0]
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ldr r0, =GPDR2
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ldr r1, =CFG_GPDR2_VAL
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str r1, [r0]
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ldr r0, =GAFR0_L
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ldr r1, =CFG_GAFR0_L_VAL
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str r1, [r0]
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ldr r0, =GAFR0_U
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ldr r1, =CFG_GAFR0_U_VAL
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str r1, [r0]
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ldr r0, =GAFR1_L
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ldr r1, =CFG_GAFR1_L_VAL
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str r1, [r0]
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ldr r0, =GAFR1_U
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ldr r1, =CFG_GAFR1_U_VAL
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str r1, [r0]
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ldr r0, =GAFR2_L
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ldr r1, =CFG_GAFR2_L_VAL
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str r1, [r0]
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ldr r0, =GAFR2_U
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ldr r1, =CFG_GAFR2_U_VAL
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str r1, [r0]
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ldr r0, =PSSR /* enable GPIO pins */
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ldr r1, =CFG_PSSR_VAL
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str r1, [r0]
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#ifdef DEBUG_BLINK_ENABLE
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/* 4th debug blink */
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bl blink
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#endif
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/* ---------------------------------------------------------------- */
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/* Enable memory interface */
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/* */
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/* The sequence below is based on the recommended init steps */
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/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
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/* Chapter 10. */
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/* ---------------------------------------------------------------- */
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/* ---------------------------------------------------------------- */
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/* Step 1: Wait for at least 200 microsedonds to allow internal */
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/* clocks to settle. Only necessary after hard reset... */
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/* FIXME: can be optimized later */
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/* ---------------------------------------------------------------- */
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
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/* so 0x300 should be plenty */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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mem_init:
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ldr r1, =MEMC_BASE /* get memory controller base addr. */
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/* ---------------------------------------------------------------- */
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/* Step 2a: Initialize Asynchronous static memory controller */
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/* ---------------------------------------------------------------- */
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/* MSC registers: timing, bus width, mem type */
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/* MSC0: nCS(0,1) */
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ldr r2, =CFG_MSC0_VAL
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str r2, [r1, #MSC0_OFFSET]
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ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
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/* that data latches */
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/* MSC1: nCS(2,3) */
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ldr r2, =CFG_MSC1_VAL
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str r2, [r1, #MSC1_OFFSET]
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ldr r2, [r1, #MSC1_OFFSET]
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/* MSC2: nCS(4,5) */
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ldr r2, =CFG_MSC2_VAL
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str r2, [r1, #MSC2_OFFSET]
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ldr r2, [r1, #MSC2_OFFSET]
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/* ---------------------------------------------------------------- */
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/* Step 2b: Initialize Card Interface */
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/* ---------------------------------------------------------------- */
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/* MECR: Memory Expansion Card Register */
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ldr r2, =CFG_MECR_VAL
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str r2, [r1, #MECR_OFFSET]
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ldr r2, [r1, #MECR_OFFSET]
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/* MCMEM0: Card Interface slot 0 timing */
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ldr r2, =CFG_MCMEM0_VAL
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str r2, [r1, #MCMEM0_OFFSET]
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ldr r2, [r1, #MCMEM0_OFFSET]
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/* MCMEM1: Card Interface slot 1 timing */
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ldr r2, =CFG_MCMEM1_VAL
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str r2, [r1, #MCMEM1_OFFSET]
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ldr r2, [r1, #MCMEM1_OFFSET]
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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ldr r2, =CFG_MCATT0_VAL
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str r2, [r1, #MCATT0_OFFSET]
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ldr r2, [r1, #MCATT0_OFFSET]
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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ldr r2, =CFG_MCATT1_VAL
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str r2, [r1, #MCATT1_OFFSET]
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ldr r2, [r1, #MCATT1_OFFSET]
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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ldr r2, =CFG_MCIO0_VAL
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str r2, [r1, #MCIO0_OFFSET]
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ldr r2, [r1, #MCIO0_OFFSET]
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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ldr r2, =CFG_MCIO1_VAL
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str r2, [r1, #MCIO1_OFFSET]
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ldr r2, [r1, #MCIO1_OFFSET]
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#ifdef DEBUG_BLINK_ENABLE
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/* 5th blink */
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bl blink
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#endif
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/* ---------------------------------------------------------------- */
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/* Step 2c: Write FLYCNFG FIXME: what's that??? */
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/* ---------------------------------------------------------------- */
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/* ---------------------------------------------------------------- */
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/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
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/* ---------------------------------------------------------------- */
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/* Before accessing MDREFR we need a valid DRI field, so we set */
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/* this to power on defaults + DRI field. */
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ldr r3, =CFG_MDREFR_VAL
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ldr r2, =0xFFF
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and r3, r3, r2
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ldr r4, =0x03ca4000
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orr r4, r4, r3
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str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r4, [r1, #MDREFR_OFFSET]
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/* Note: preserve the mdrefr value in r4 */
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/* ---------------------------------------------------------------- */
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/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
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/* ---------------------------------------------------------------- */
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/* Initialize SXCNFG register. Assert the enable bits */
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/* Write SXMRS to cause an MRS command to all enabled banks of */
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/* synchronous static memory. Note that SXLCR need not be written */
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/* at this time. */
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/* FIXME: we use async mode for now */
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/* ---------------------------------------------------------------- */
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/* Step 4: Initialize SDRAM */
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/* ---------------------------------------------------------------- */
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/* set MDREFR according to user define with exception of a few bits */
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ldr r4, =CFG_MDREFR_VAL
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orr r4, r4, #(MDREFR_SLFRSH)
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bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
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str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r4, [r1, #MDREFR_OFFSET]
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/* Step 4b: de-assert MDREFR:SLFRSH. */
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bic r4, r4, #(MDREFR_SLFRSH)
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str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r4, [r1, #MDREFR_OFFSET]
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/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
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ldr r4, =CFG_MDREFR_VAL
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str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r4, [r1, #MDREFR_OFFSET]
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/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
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/* configure but not enable each SDRAM partition pair. */
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ldr r4, =CFG_MDCNFG_VAL
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bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
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str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
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ldr r4, [r1, #MDCNFG_OFFSET]
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/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
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/* 100..200 <20>sec. */
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
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/* so 0x300 should be plenty */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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/* Step 4f: Trigger a number (usually 8) refresh cycles by */
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/* attempting non-burst read or write accesses to disabled */
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/* SDRAM, as commonly specified in the power up sequence */
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/* documented in SDRAM data sheets. The address(es) used */
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/* for this purpose must not be cacheable. */
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ldr r3, =CFG_DRAM_BASE
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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str r2, [r3]
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/* Step 4g: Write MDCNFG with enable bits asserted */
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/* (MDCNFG:DEx set to 1). */
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ldr r3, [r1, #MDCNFG_OFFSET]
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orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
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str r3, [r1, #MDCNFG_OFFSET]
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/* Step 4h: Write MDMRS. */
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ldr r2, =CFG_MDMRS_VAL
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str r2, [r1, #MDMRS_OFFSET]
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/* We are finished with Intel's memory controller initialisation */
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#if 0
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/* FIXME turn on serial ports */
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/* look into moving this to board_init() */
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ldr r2, =(PXA_CS5_PHYS + 0x03C0002c)
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mov r3, #0x13
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str r3, [r2]
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#endif
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#ifdef DEBUG_BLINK_ENABLE
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/* 6th blink */
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bl blink
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#endif
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/* ---------------------------------------------------------------- */
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/* Disable (mask) all interrupts at interrupt controller */
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/* ---------------------------------------------------------------- */
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initirqs:
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mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
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ldr r2, =ICLR
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str r1, [r2]
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ldr r2, =ICMR /* mask all interrupts at the controller */
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str r1, [r2]
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/* ---------------------------------------------------------------- */
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/* Clock initialisation */
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/* ---------------------------------------------------------------- */
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initclks:
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/* Disable the peripheral clocks, and set the core clock frequency */
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/* (hard-coding at 398.12MHz for now). */
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/* Turn Off ALL on-chip peripheral clocks for re-configuration */
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/* Note: See label 'ENABLECLKS' for the re-enabling */
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#if 0
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ldr r1, =CKEN
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mov r2, #0
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str r2, [r1]
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/* default value in case no valid rotary switch setting is found */
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ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
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/* ... and write the core clock config register */
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ldr r1, =CCCR
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str r2, [r1]
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#endif
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#ifdef RTC
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/* enable the 32Khz oscillator for RTC and PowerManager */
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ldr r1, =OSCC
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mov r2, #OSCC_OON
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str r2, [r1]
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/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
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/* has settled. */
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60:
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ldr r2, [r1]
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ands r2, r2, #1
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beq 60b
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#endif
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/* ---------------------------------------------------------------- */
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/* */
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/* ---------------------------------------------------------------- */
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/* Save SDRAM size */
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ldr r1, =DRAM_SIZE
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str r8, [r1]
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/* Interrupt init: Mask all interrupts */
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ldr r0, =ICMR /* enable no sources */
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mov r1, #0
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str r1, [r0]
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/* FIXME */
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#define NODEBUG
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#ifdef NODEBUG
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/*Disable software and data breakpoints */
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mov r0,#0
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mcr p15,0,r0,c14,c8,0 /* ibcr0 */
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mcr p15,0,r0,c14,c9,0 /* ibcr1 */
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mcr p15,0,r0,c14,c4,0 /* dbcon */
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/*Enable all debug functionality */
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mov r0,#0x80000000
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mcr p14,0,r0,c10,c0,0 /* dcsr */
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#endif
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/* ---------------------------------------------------------------- */
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/* End memsetup */
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/* ---------------------------------------------------------------- */
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#ifdef DEBUG_BLINK_ENABLE
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/* 7th blink */
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bl blink
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#endif
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endlowlevel_init:
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mov pc, r10
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#ifdef DEBUG_BLINK_ENABLE
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/* debug LED code */
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/* delay about 200ms */
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delay:
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/* reset OSCR to 0 */
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ldr r8, =OSCR
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mov r9, #0
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str r9, [r8]
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/* make sure new value has stuck */
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1:
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ldr r8, =OSCR
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ldr r9, [r8]
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mov r8, #0x10000
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cmp r9, r8
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bgt 1b
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/* now, wait for delay to expire */
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1:
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ldr r8, =OSCR
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ldr r9, [r8]
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mov r8, #0xd4000
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cmp r8, r9
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bgt 1b
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mov pc, lr
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/* blink code -- trashes r7, r8, r9 */
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.globl blink
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blink:
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mov r7, lr
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/* set GPIO10 as outout */
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ldr r8, =GPDR0
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ldr r9, [r8]
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orr r9, r9, #(1<<10)
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str r9, [r8]
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/* turn LED off */
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mov r9, #(1<<10)
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ldr r8, =GPCR0
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str r9, [r8]
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bl delay
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/* turn LED on */
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mov r9, #(1<<10)
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ldr r8, =GPSR0
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str r9, [r8]
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bl delay
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/* turn LED off */
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mov r9, #(1<<10)
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ldr r8, =GPCR0
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str r9, [r8]
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mov pc, r7
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#endif
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