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https://github.com/brain-hackers/u-boot-brain
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e5ffa4bb62
According to Atom E6xx datasheet, setting VGA Disable (bit17) of Graphics Controller register (offset 0x50) prevents IGD (D2:F0) from reporting itself as a VGA display controller class in the PCI configuration space, and should also prevent it from responding to VGA legacy memory range and I/O addresses. However test result shows that with just VGA Disable bit set and a PCIe graphics card connected to one of the PCIe controllers on the E6xx, accessing the VGA legacy space still causes system hang. After a number of attempts, it turns out besides VGA Disable bit, the SDVO (D3:F0) device should be disabled to make it work. To simplify, use the Function Disable register (offset 0xc4) to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these two devices will be completely disabled (invisible in the PCI configuration space) unless a system reset is performed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
54 lines
807 B
C
54 lines
807 B
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_ARCH_TNC_H_
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#define _X86_ARCH_TNC_H_
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/* IGD Function Disable Register */
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#define IGD_FD 0xc4
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#define FUNC_DISABLE 0x00000001
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/* Memory BAR Enable */
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#define MEM_BAR_EN 0x00000001
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/* LPC PCI Configuration Registers */
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#define LPC_RCBA 0xf0
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/* Root Complex Register Block */
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struct tnc_rcba {
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u32 rctl;
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u32 esd;
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u32 rsvd1[2];
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u32 hdd;
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u32 rsvd2;
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u32 hdba;
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u32 rsvd3[3129];
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u32 d31ip;
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u32 rsvd4[3];
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u32 d27ip;
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u32 rsvd5;
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u32 d02ip;
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u32 rsvd6;
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u32 d26ip;
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u32 d25ip;
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u32 d24ip;
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u32 d23ip;
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u32 d03ip;
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u32 rsvd7[3];
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u16 d31ir;
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u16 rsvd8[3];
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u16 d27ir;
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u16 d26ir;
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u16 d25ir;
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u16 d24ir;
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u16 d23ir;
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u16 rsvd9[7];
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u16 d02ir;
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u16 d03ir;
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};
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#endif /* _X86_ARCH_TNC_H_ */
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