Philipp Tomsich 434d5a00a4 rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL ... The device-tree node for the PMU clk controller assigns to its parent (i.e. PLL_PPLL) even though this clock currently is set up statically by an init-function. In order to avoid unexpected failures, a simple implementation of set_rate (which accepts requests, but notifies the caller of the preset frequency in its return value) and get_rate (which always returns the preset frequency) are added. Note that this is required for the RK808 PMIC to probe successfully on the RK3399-Q7, following the support for the assigned-clocks property. References: commit f4fcba5c5b ("clk: implement clk_set_defaults()") Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>		2018-02-24 18:50:03 +01:00
..
clk_rk322x.c	clk: rockchip: Add rk322x gamc clock support	2018-01-28 17:12:38 +01:00
clk_rk3036.c	rockchip: clk: bind reset driver	2018-01-09 11:13:32 +01:00
clk_rk3128.c	rockchip: rk3128: add clock driver	2017-11-30 22:55:26 +01:00
clk_rk3188.c	rockchip: clk: bind reset driver	2018-01-09 11:13:32 +01:00
clk_rk3288.c	rockchip: clk: guard set_parent implementations against OF_PLATDATA	2018-01-28 17:12:39 +01:00
clk_rk3328.c	clk: rockchip: Add rk3328 gamc clock support	2018-01-28 17:12:37 +01:00
clk_rk3368.c	rockchip: clk: rk3368: handle clk_enable requests for GMAC	2018-02-24 18:46:45 +01:00
clk_rk3399.c	rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL	2018-02-24 18:50:03 +01:00
clk_rv1108.c	rockchip: clk: bind reset driver	2018-01-09 11:13:32 +01:00
Makefile	rockchip: rk3128: add clock driver	2017-11-30 22:55:26 +01:00