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https://github.com/brain-hackers/u-boot-brain
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aee0013e53
Currently by running the following test: => setenv bootcmd reset => save => reset , we observe a hang after approximately 20-30 minutes of stress reboot test. Investigation of this issue revealed that when a single DDR chip select is used, the hang does not happen. It only happens when the two chip selects are active. MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence": "The controller must keep the memory lines quiet (except for CK) for the ZQ calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256 for other ZQCL and 64 for ZQCS)." According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL: "Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines. Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)" So make sure to activate one chip select at time (CS0 first and then CS1 later), so that the required JEDEC delay is respected for each chip select. With this change applied the board has gone through three days of reboot stress test without any hang. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
85 lines
2.2 KiB
INI
85 lines
2.2 KiB
INI
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer doc/README.imximage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x53fa8554 0x00300000
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DATA 4 0x53fa8558 0x00300040
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DATA 4 0x53fa8560 0x00300000
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DATA 4 0x53fa8564 0x00300040
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DATA 4 0x53fa8568 0x00300040
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DATA 4 0x53fa8570 0x00300000
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DATA 4 0x53fa8574 0x00300000
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DATA 4 0x53fa8578 0x00300000
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DATA 4 0x53fa857c 0x00300040
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DATA 4 0x53fa8580 0x00300040
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DATA 4 0x53fa8584 0x00300000
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DATA 4 0x53fa8588 0x00300000
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DATA 4 0x53fa8590 0x00300040
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DATA 4 0x53fa8594 0x00300000
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DATA 4 0x53fa86f0 0x00300000
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DATA 4 0x53fa86f4 0x00000000
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DATA 4 0x53fa86fc 0x00000000
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DATA 4 0x53fa8714 0x00000000
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DATA 4 0x53fa8718 0x00300000
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DATA 4 0x53fa871c 0x00300000
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DATA 4 0x53fa8720 0x00300000
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DATA 4 0x53fa8724 0x04000000
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DATA 4 0x53fa8728 0x00300000
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DATA 4 0x53fa872c 0x00300000
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DATA 4 0x63fd9088 0x35343535
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DATA 4 0x63fd9090 0x4d444c44
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DATA 4 0x63fd907c 0x01370138
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DATA 4 0x63fd9080 0x013b013c
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DATA 4 0x63fd9018 0x00011740
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DATA 4 0x63fd9000 0x83190000
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DATA 4 0x63fd900c 0x9f5152e3
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DATA 4 0x63fd9010 0xb68e8a63
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DATA 4 0x63fd9014 0x01ff00db
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DATA 4 0x63fd902c 0x000026d2
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DATA 4 0x63fd9030 0x009f0e21
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DATA 4 0x63fd9008 0x12273030
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DATA 4 0x63fd9004 0x0002002d
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DATA 4 0x63fd901c 0x00008032
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DATA 4 0x63fd901c 0x00008033
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DATA 4 0x63fd901c 0x00028031
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DATA 4 0x63fd901c 0x052080b0
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DATA 4 0x63fd901c 0x04008040
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DATA 4 0x63fd9000 0xc3190000
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DATA 4 0x63fd901c 0x0000803a
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DATA 4 0x63fd901c 0x0000803b
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DATA 4 0x63fd901c 0x00028039
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DATA 4 0x63fd901c 0x05208138
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DATA 4 0x63fd901c 0x04008048
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DATA 4 0x63fd9020 0x00005800
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DATA 4 0x63fd9040 0x05380003
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DATA 4 0x63fd9058 0x00022227
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DATA 4 0x63fd901c 0x00000000
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