mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-15 15:46:16 +09:00
39ff7d5f4c
This patch introduces a weak default function for post_hotkey_pressed(), returning 0, for boards without hotkey support. The long-running tests won't be started on those boards. This default function was implemented in many board directories. By implementing this weak default we can remove all those duplicate versions. Boards with hotkey support, can override this weak default function by defining one in their board specific code. Signed-off-by: Stefan Roese <sr@denx.de>
271 lines
9.6 KiB
C
271 lines
9.6 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <mpc8xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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int fec8xx_miiphy_write(char *devname, unsigned char addr,
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unsigned char reg, unsigned short value);
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/*********************************************************************/
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/* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B) */
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/*********************************************************************/
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const uint sdram_init_upm_table[] = {
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/* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
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/* NOP - Precharge - AutoRefr - NOP - NOP */
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/* NOP - AutoRefr - NOP */
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/* NOP - NOP - LoadModeR - NOP - Active */
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/* Position of Single Read */
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0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
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0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
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/* Burst Read. (offset 8 in UPMA RAM) */
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/* Cycle lent for Initialisation WV */
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0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Single Write. (offset 18 in UPMA RAM) */
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Burst Write. (offset 20 in UPMA RAM) */
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Refresh (offset 30 in UPMA RAM) */
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0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
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0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF,
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/* Exception. (offset 3c in UPMA RAM) */
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0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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};
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/*********************************************************************/
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/* UPMA initilization table. */
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/*********************************************************************/
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const uint sdram_upm_table[] = {
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/* single read. (offset 0 in UPMA RAM) */
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0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x05-0x07 new WV */
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/* Burst Read. (offset 8 in UPMA RAM) */
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0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
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0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Single Write. (offset 18 in UPMA RAM) */
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0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
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0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Burst Write. (offset 20 in UPMA RAM) */
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0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
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0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Refresh (offset 30 in UPMA RAM) */
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0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
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0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF,
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/* Exception. (offset 3c in UPMA RAM) */
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0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
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};
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/*********************************************************************/
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/* UPMB initilization table. */
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/*********************************************************************/
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const uint mpm_upm_table[] = {
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/* single read. (offset 0 in upm RAM) */
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0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
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0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* burst read. (Offset 8 in upm RAM) */
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* single write. (Offset 0x18 in upm RAM) */
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0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
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0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
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/* burst write. (Offset 0x20 in upm RAM) */
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Refresh cycle, offset 0x30 */
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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/* Exception, 0ffset 0x3C */
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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};
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int board_switch(void)
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{
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volatile pcmconf8xx_t *pcmp;
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pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
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return ((pcmp->pcmc_pipr >> 24) & 0xf);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming UC100");
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} else {
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puts(str);
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}
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printf (" (SWITCH=%1X)\n", board_switch());
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return 0;
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}
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/*
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* Initialize SDRAM
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*/
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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/*---------------------------------------------------------------------*/
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/* Initialize the UPMA/UPMB registers with the appropriate table. */
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/*---------------------------------------------------------------------*/
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upmconfig (UPMA, (uint *) sdram_init_upm_table,
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sizeof (sdram_init_upm_table) / sizeof (uint));
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upmconfig (UPMB, (uint *) mpm_upm_table,
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sizeof (mpm_upm_table) / sizeof (uint));
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/*---------------------------------------------------------------------*/
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/* Memory Periodic Timer Prescaler: divide by 16 */
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/*---------------------------------------------------------------------*/
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memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
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memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
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memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL;
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/*---------------------------------------------------------------------*/
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/* Initialize the Memory Controller registers, MPTPR, Chip Select 1 */
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/* for SDRAM */
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/* */
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/* NOTE: The refresh rate in MAMR reg is set according to the lowest */
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/* clock rate (16.67MHz) to allow proper operation for all ADS */
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/* clock frequencies. */
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/*---------------------------------------------------------------------*/
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memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
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memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
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/*-------------------------------------------------------------------*/
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/* Wait at least 200 usec for DRAM to stabilize, this magic number */
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/* obtained from the init code. */
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/*-------------------------------------------------------------------*/
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udelay(200);
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memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
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memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
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memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
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/*---------------------------------------------------------------------*/
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/* run MRS command in location 5-8 of UPMB. */
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/*---------------------------------------------------------------------*/
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memctl->memc_mar = 0x88;
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/* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
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memctl->memc_mcr = 0x80002100;
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/* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
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udelay(200);
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/*---------------------------------------------------------------------*/
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/* Initialisation for normal access WV */
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/*---------------------------------------------------------------------*/
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/*---------------------------------------------------------------------*/
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/* Initialize the UPMA register with the appropriate table. */
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/*---------------------------------------------------------------------*/
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upmconfig (UPMA, (uint *) sdram_upm_table,
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sizeof (sdram_upm_table) / sizeof (uint));
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/*---------------------------------------------------------------------*/
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/* rerstore MBMR value (4-beat refresh burst.) */
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/*---------------------------------------------------------------------*/
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memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
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udelay(200);
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return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
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}
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int misc_init_r (void)
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{
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uchar val;
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/*
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* Make sure that RTC has clock output enabled (triggers watchdog!)
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*/
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val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D);
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val |= 0x80;
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i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val);
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/*
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* Configure PHY to setup LED's correctly and use 100MBit, FD
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*/
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mii_init();
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/* disable auto-negotiation, 100mbit, full-duplex */
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fec8xx_miiphy_write(NULL, 0, PHY_BMCR, 0x2100);
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/* set LED's to Link, Transmit, Receive */
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fec8xx_miiphy_write(NULL, 0, PHY_FCSCR, 0x4122);
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return 0;
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}
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