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![Simon Glass](/assets/img/avatar_default.png)
These functions are CPU-related and do not use driver model. Move them to cpu_func.h Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
782 lines
20 KiB
C
782 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2011 PetaLogix
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* Copyright (C) 2010 Xilinx, Inc. All rights reserved.
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*/
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#include <config.h>
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <net.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <phy.h>
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#include <miiphy.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Link setup */
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#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
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#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
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#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
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#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
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/* Interrupt Status/Enable/Mask Registers bit definitions */
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#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
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#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
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/* Receive Configuration Word 1 (RCW1) Register bit definitions */
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#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
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/* Transmitter Configuration (TC) Register bit definitions */
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#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
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#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
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/* MDIO Management Configuration (MC) Register bit definitions */
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#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
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/* MDIO Management Control Register (MCR) Register bit definitions */
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#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
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#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
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#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
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#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
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#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
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#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
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#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
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#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
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#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
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#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
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/* DMA macros */
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/* Bitmasks of XAXIDMA_CR_OFFSET register */
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#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
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#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
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/* Bitmasks of XAXIDMA_SR_OFFSET register */
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#define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
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/* Bitmask for interrupts */
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#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
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#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
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#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
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/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
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#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
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#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
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#define DMAALIGN 128
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static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
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/* Reflect dma offsets */
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struct axidma_reg {
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u32 control; /* DMACR */
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u32 status; /* DMASR */
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u32 current; /* CURDESC low 32 bit */
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u32 current_hi; /* CURDESC high 32 bit */
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u32 tail; /* TAILDESC low 32 bit */
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u32 tail_hi; /* TAILDESC high 32 bit */
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};
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/* Private driver structures */
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struct axidma_priv {
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struct axidma_reg *dmatx;
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struct axidma_reg *dmarx;
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int phyaddr;
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struct axi_regs *iobase;
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phy_interface_t interface;
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struct phy_device *phydev;
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struct mii_dev *bus;
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u8 eth_hasnobuf;
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int phy_of_handle;
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};
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/* BD descriptors */
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struct axidma_bd {
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u32 next; /* Next descriptor pointer */
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u32 reserved1;
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u32 phys; /* Buffer address */
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u32 reserved2;
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u32 reserved3;
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u32 reserved4;
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u32 cntrl; /* Control */
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u32 status; /* Status */
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u32 app0;
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u32 app1; /* TX start << 16 | insert */
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u32 app2; /* TX csum seed */
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u32 app3;
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u32 app4;
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u32 sw_id_offset;
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u32 reserved5;
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u32 reserved6;
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};
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/* Static BDs - driver uses only one BD */
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static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
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static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
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struct axi_regs {
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u32 reserved[3];
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u32 is; /* 0xC: Interrupt status */
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u32 reserved2;
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u32 ie; /* 0x14: Interrupt enable */
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u32 reserved3[251];
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u32 rcw1; /* 0x404: Rx Configuration Word 1 */
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u32 tc; /* 0x408: Tx Configuration */
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u32 reserved4;
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u32 emmc; /* 0x410: EMAC mode configuration */
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u32 reserved5[59];
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u32 mdio_mc; /* 0x500: MII Management Config */
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u32 mdio_mcr; /* 0x504: MII Management Control */
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u32 mdio_mwd; /* 0x508: MII Management Write Data */
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u32 mdio_mrd; /* 0x50C: MII Management Read Data */
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u32 reserved6[124];
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u32 uaw0; /* 0x700: Unicast address word 0 */
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u32 uaw1; /* 0x704: Unicast address word 1 */
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};
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/* Use MII register 1 (MII status register) to detect PHY */
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#define PHY_DETECT_REG 1
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/*
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* Mask used to verify certain PHY features (or register contents)
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* in the register above:
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* 0x1000: 10Mbps full duplex support
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* 0x0800: 10Mbps half duplex support
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* 0x0008: Auto-negotiation support
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*/
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#define PHY_DETECT_MASK 0x1808
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static inline int mdio_wait(struct axi_regs *regs)
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{
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u32 timeout = 200;
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/* Wait till MDIO interface is ready to accept a new transaction. */
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while (timeout && (!(readl(®s->mdio_mcr)
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& XAE_MDIO_MCR_READY_MASK))) {
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timeout--;
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udelay(1);
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}
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return 1;
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}
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return 0;
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}
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/**
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* axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
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* @bd: pointer to BD descriptor structure
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* @desc: Address offset of DMA descriptors
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*
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* This function writes the value into the corresponding Axi DMA register.
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*/
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static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
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{
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#if defined(CONFIG_PHYS_64BIT)
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writeq(bd, desc);
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#else
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writel((u32)bd, desc);
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#endif
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}
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static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
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u16 *val)
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{
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struct axi_regs *regs = priv->iobase;
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u32 mdioctrlreg = 0;
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if (mdio_wait(regs))
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return 1;
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mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
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XAE_MDIO_MCR_PHYAD_MASK) |
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((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
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& XAE_MDIO_MCR_REGAD_MASK) |
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XAE_MDIO_MCR_INITIATE_MASK |
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XAE_MDIO_MCR_OP_READ_MASK;
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writel(mdioctrlreg, ®s->mdio_mcr);
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if (mdio_wait(regs))
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return 1;
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/* Read data */
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*val = readl(®s->mdio_mrd);
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return 0;
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}
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static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
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u32 data)
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{
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struct axi_regs *regs = priv->iobase;
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u32 mdioctrlreg = 0;
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if (mdio_wait(regs))
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return 1;
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mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
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XAE_MDIO_MCR_PHYAD_MASK) |
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((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
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& XAE_MDIO_MCR_REGAD_MASK) |
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XAE_MDIO_MCR_INITIATE_MASK |
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XAE_MDIO_MCR_OP_WRITE_MASK;
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/* Write data */
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writel(data, ®s->mdio_mwd);
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writel(mdioctrlreg, ®s->mdio_mcr);
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if (mdio_wait(regs))
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return 1;
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return 0;
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}
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static int axiemac_phy_init(struct udevice *dev)
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{
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u16 phyreg;
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u32 i, ret;
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struct axidma_priv *priv = dev_get_priv(dev);
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struct axi_regs *regs = priv->iobase;
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struct phy_device *phydev;
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u32 supported = SUPPORTED_10baseT_Half |
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SUPPORTED_10baseT_Full |
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SUPPORTED_100baseT_Half |
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SUPPORTED_100baseT_Full |
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SUPPORTED_1000baseT_Half |
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SUPPORTED_1000baseT_Full;
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/* Set default MDIO divisor */
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writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
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if (priv->phyaddr == -1) {
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/* Detect the PHY address */
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for (i = 31; i >= 0; i--) {
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ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
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if (!ret && (phyreg != 0xFFFF) &&
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((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
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/* Found a valid PHY address */
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priv->phyaddr = i;
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debug("axiemac: Found valid phy address, %x\n",
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i);
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break;
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}
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}
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}
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/* Interface - look at tsec */
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phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
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phydev->supported &= supported;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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if (priv->phy_of_handle)
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priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
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phy_config(phydev);
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return 0;
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}
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/* Setting axi emac and phy to proper setting */
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static int setup_phy(struct udevice *dev)
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{
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u16 temp;
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u32 speed, emmc_reg, ret;
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struct axidma_priv *priv = dev_get_priv(dev);
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struct axi_regs *regs = priv->iobase;
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struct phy_device *phydev = priv->phydev;
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if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
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/*
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* In SGMII cases the isolate bit might set
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* after DMA and ethernet resets and hence
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* check and clear if set.
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*/
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ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
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if (ret)
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return 0;
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if (temp & BMCR_ISOLATE) {
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temp &= ~BMCR_ISOLATE;
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ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
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if (ret)
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return 0;
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}
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}
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if (phy_startup(phydev)) {
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printf("axiemac: could not initialize PHY %s\n",
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phydev->dev->name);
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return 0;
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}
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if (!phydev->link) {
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printf("%s: No link.\n", phydev->dev->name);
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return 0;
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}
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switch (phydev->speed) {
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case 1000:
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speed = XAE_EMMC_LINKSPD_1000;
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break;
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case 100:
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speed = XAE_EMMC_LINKSPD_100;
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break;
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case 10:
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speed = XAE_EMMC_LINKSPD_10;
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break;
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default:
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return 0;
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}
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/* Setup the emac for the phy speed */
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emmc_reg = readl(®s->emmc);
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emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
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emmc_reg |= speed;
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/* Write new speed setting out to Axi Ethernet */
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writel(emmc_reg, ®s->emmc);
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/*
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* Setting the operating speed of the MAC needs a delay. There
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* doesn't seem to be register to poll, so please consider this
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* during your application design.
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*/
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udelay(1);
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return 1;
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}
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/* STOP DMA transfers */
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static void axiemac_stop(struct udevice *dev)
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{
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struct axidma_priv *priv = dev_get_priv(dev);
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u32 temp;
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/* Stop the hardware */
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temp = readl(&priv->dmatx->control);
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temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
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writel(temp, &priv->dmatx->control);
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temp = readl(&priv->dmarx->control);
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temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
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writel(temp, &priv->dmarx->control);
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debug("axiemac: Halted\n");
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}
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static int axi_ethernet_init(struct axidma_priv *priv)
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{
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struct axi_regs *regs = priv->iobase;
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int err;
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/*
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* Check the status of the MgtRdy bit in the interrupt status
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* registers. This must be done to allow the MGT clock to become stable
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* for the Sgmii and 1000BaseX PHY interfaces. No other register reads
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* will be valid until this bit is valid.
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* The bit is always a 1 for all other PHY interfaces.
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* Interrupt status and enable registers are not available in non
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* processor mode and hence bypass in this mode
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*/
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if (!priv->eth_hasnobuf) {
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err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
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true, 200, false);
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if (err) {
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printf("%s: Timeout\n", __func__);
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return 1;
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}
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/*
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* Stop the device and reset HW
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* Disable interrupts
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*/
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writel(0, ®s->ie);
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}
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/* Disable the receiver */
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writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
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/*
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* Stopping the receiver in mid-packet causes a dropped packet
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* indication from HW. Clear it.
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*/
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if (!priv->eth_hasnobuf) {
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/* Set the interrupt status register to clear the interrupt */
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writel(XAE_INT_RXRJECT_MASK, ®s->is);
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}
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/* Setup HW */
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/* Set default MDIO divisor */
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writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
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debug("axiemac: InitHw done\n");
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return 0;
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}
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static int axiemac_write_hwaddr(struct udevice *dev)
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{
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct axidma_priv *priv = dev_get_priv(dev);
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struct axi_regs *regs = priv->iobase;
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/* Set the MAC address */
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int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
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(pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
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writel(val, ®s->uaw0);
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val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
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val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
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writel(val, ®s->uaw1);
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return 0;
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}
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/* Reset DMA engine */
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static void axi_dma_init(struct axidma_priv *priv)
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{
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u32 timeout = 500;
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/* Reset the engine so the hardware starts from a known state */
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writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
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writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
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/* At the initialization time, hardware should finish reset quickly */
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while (timeout--) {
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/* Check transmit/receive channel */
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/* Reset is done when the reset bit is low */
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if (!((readl(&priv->dmatx->control) |
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readl(&priv->dmarx->control))
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& XAXIDMA_CR_RESET_MASK)) {
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break;
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}
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}
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if (!timeout)
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printf("%s: Timeout\n", __func__);
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}
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static int axiemac_start(struct udevice *dev)
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{
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struct axidma_priv *priv = dev_get_priv(dev);
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struct axi_regs *regs = priv->iobase;
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u32 temp;
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debug("axiemac: Init started\n");
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/*
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* Initialize AXIDMA engine. AXIDMA engine must be initialized before
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* AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
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* reset, and since AXIDMA reset line is connected to AxiEthernet, this
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* would ensure a reset of AxiEthernet.
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*/
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axi_dma_init(priv);
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/* Initialize AxiEthernet hardware. */
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if (axi_ethernet_init(priv))
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return -1;
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/* Disable all RX interrupts before RxBD space setup */
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temp = readl(&priv->dmarx->control);
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temp &= ~XAXIDMA_IRQ_ALL_MASK;
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writel(temp, &priv->dmarx->control);
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|
/* Start DMA RX channel. Now it's ready to receive data.*/
|
|
axienet_dma_write(&rx_bd, &priv->dmarx->current);
|
|
|
|
/* Setup the BD. */
|
|
memset(&rx_bd, 0, sizeof(rx_bd));
|
|
rx_bd.next = (u32)&rx_bd;
|
|
rx_bd.phys = (u32)&rxframe;
|
|
rx_bd.cntrl = sizeof(rxframe);
|
|
/* Flush the last BD so DMA core could see the updates */
|
|
flush_cache((u32)&rx_bd, sizeof(rx_bd));
|
|
|
|
/* It is necessary to flush rxframe because if you don't do it
|
|
* then cache can contain uninitialized data */
|
|
flush_cache((u32)&rxframe, sizeof(rxframe));
|
|
|
|
/* Start the hardware */
|
|
temp = readl(&priv->dmarx->control);
|
|
temp |= XAXIDMA_CR_RUNSTOP_MASK;
|
|
writel(temp, &priv->dmarx->control);
|
|
|
|
/* Rx BD is ready - start */
|
|
axienet_dma_write(&rx_bd, &priv->dmarx->tail);
|
|
|
|
/* Enable TX */
|
|
writel(XAE_TC_TX_MASK, ®s->tc);
|
|
/* Enable RX */
|
|
writel(XAE_RCW1_RX_MASK, ®s->rcw1);
|
|
|
|
/* PHY setup */
|
|
if (!setup_phy(dev)) {
|
|
axiemac_stop(dev);
|
|
return -1;
|
|
}
|
|
|
|
debug("axiemac: Init complete\n");
|
|
return 0;
|
|
}
|
|
|
|
static int axiemac_send(struct udevice *dev, void *ptr, int len)
|
|
{
|
|
struct axidma_priv *priv = dev_get_priv(dev);
|
|
u32 timeout;
|
|
|
|
if (len > PKTSIZE_ALIGN)
|
|
len = PKTSIZE_ALIGN;
|
|
|
|
/* Flush packet to main memory to be trasfered by DMA */
|
|
flush_cache((u32)ptr, len);
|
|
|
|
/* Setup Tx BD */
|
|
memset(&tx_bd, 0, sizeof(tx_bd));
|
|
/* At the end of the ring, link the last BD back to the top */
|
|
tx_bd.next = (u32)&tx_bd;
|
|
tx_bd.phys = (u32)ptr;
|
|
/* Save len */
|
|
tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
|
|
XAXIDMA_BD_CTRL_TXEOF_MASK;
|
|
|
|
/* Flush the last BD so DMA core could see the updates */
|
|
flush_cache((u32)&tx_bd, sizeof(tx_bd));
|
|
|
|
if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
|
|
u32 temp;
|
|
axienet_dma_write(&tx_bd, &priv->dmatx->current);
|
|
/* Start the hardware */
|
|
temp = readl(&priv->dmatx->control);
|
|
temp |= XAXIDMA_CR_RUNSTOP_MASK;
|
|
writel(temp, &priv->dmatx->control);
|
|
}
|
|
|
|
/* Start transfer */
|
|
axienet_dma_write(&tx_bd, &priv->dmatx->tail);
|
|
|
|
/* Wait for transmission to complete */
|
|
debug("axiemac: Waiting for tx to be done\n");
|
|
timeout = 200;
|
|
while (timeout && (!(readl(&priv->dmatx->status) &
|
|
(XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
|
|
timeout--;
|
|
udelay(1);
|
|
}
|
|
if (!timeout) {
|
|
printf("%s: Timeout\n", __func__);
|
|
return 1;
|
|
}
|
|
|
|
debug("axiemac: Sending complete\n");
|
|
return 0;
|
|
}
|
|
|
|
static int isrxready(struct axidma_priv *priv)
|
|
{
|
|
u32 status;
|
|
|
|
/* Read pending interrupts */
|
|
status = readl(&priv->dmarx->status);
|
|
|
|
/* Acknowledge pending interrupts */
|
|
writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
|
|
|
|
/*
|
|
* If Reception done interrupt is asserted, call RX call back function
|
|
* to handle the processed BDs and then raise the according flag.
|
|
*/
|
|
if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
|
|
return 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
u32 length;
|
|
struct axidma_priv *priv = dev_get_priv(dev);
|
|
u32 temp;
|
|
|
|
/* Wait for an incoming packet */
|
|
if (!isrxready(priv))
|
|
return -1;
|
|
|
|
debug("axiemac: RX data ready\n");
|
|
|
|
/* Disable IRQ for a moment till packet is handled */
|
|
temp = readl(&priv->dmarx->control);
|
|
temp &= ~XAXIDMA_IRQ_ALL_MASK;
|
|
writel(temp, &priv->dmarx->control);
|
|
if (!priv->eth_hasnobuf)
|
|
length = rx_bd.app4 & 0xFFFF; /* max length mask */
|
|
else
|
|
length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
|
|
|
|
#ifdef DEBUG
|
|
print_buffer(&rxframe, &rxframe[0], 1, length, 16);
|
|
#endif
|
|
|
|
*packetp = rxframe;
|
|
return length;
|
|
}
|
|
|
|
static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
{
|
|
struct axidma_priv *priv = dev_get_priv(dev);
|
|
|
|
#ifdef DEBUG
|
|
/* It is useful to clear buffer to be sure that it is consistent */
|
|
memset(rxframe, 0, sizeof(rxframe));
|
|
#endif
|
|
/* Setup RxBD */
|
|
/* Clear the whole buffer and setup it again - all flags are cleared */
|
|
memset(&rx_bd, 0, sizeof(rx_bd));
|
|
rx_bd.next = (u32)&rx_bd;
|
|
rx_bd.phys = (u32)&rxframe;
|
|
rx_bd.cntrl = sizeof(rxframe);
|
|
|
|
/* Write bd to HW */
|
|
flush_cache((u32)&rx_bd, sizeof(rx_bd));
|
|
|
|
/* It is necessary to flush rxframe because if you don't do it
|
|
* then cache will contain previous packet */
|
|
flush_cache((u32)&rxframe, sizeof(rxframe));
|
|
|
|
/* Rx BD is ready - start again */
|
|
axienet_dma_write(&rx_bd, &priv->dmarx->tail);
|
|
|
|
debug("axiemac: RX completed, framelength = %d\n", length);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
|
|
int devad, int reg)
|
|
{
|
|
int ret;
|
|
u16 value;
|
|
|
|
ret = phyread(bus->priv, addr, reg, &value);
|
|
debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
|
|
value, ret);
|
|
return value;
|
|
}
|
|
|
|
static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
|
|
int reg, u16 value)
|
|
{
|
|
debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
|
|
return phywrite(bus->priv, addr, reg, value);
|
|
}
|
|
|
|
static int axi_emac_probe(struct udevice *dev)
|
|
{
|
|
struct axidma_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
|
|
priv->bus = mdio_alloc();
|
|
priv->bus->read = axiemac_miiphy_read;
|
|
priv->bus->write = axiemac_miiphy_write;
|
|
priv->bus->priv = priv;
|
|
|
|
ret = mdio_register_seq(priv->bus, dev->seq);
|
|
if (ret)
|
|
return ret;
|
|
|
|
axiemac_phy_init(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int axi_emac_remove(struct udevice *dev)
|
|
{
|
|
struct axidma_priv *priv = dev_get_priv(dev);
|
|
|
|
free(priv->phydev);
|
|
mdio_unregister(priv->bus);
|
|
mdio_free(priv->bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct eth_ops axi_emac_ops = {
|
|
.start = axiemac_start,
|
|
.send = axiemac_send,
|
|
.recv = axiemac_recv,
|
|
.free_pkt = axiemac_free_pkt,
|
|
.stop = axiemac_stop,
|
|
.write_hwaddr = axiemac_write_hwaddr,
|
|
};
|
|
|
|
static int axi_emac_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct axidma_priv *priv = dev_get_priv(dev);
|
|
int node = dev_of_offset(dev);
|
|
int offset = 0;
|
|
const char *phy_mode;
|
|
|
|
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
|
|
priv->iobase = (struct axi_regs *)pdata->iobase;
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
|
|
"axistream-connected");
|
|
if (offset <= 0) {
|
|
printf("%s: axistream is not found\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
|
|
offset, "reg");
|
|
if (!priv->dmatx) {
|
|
printf("%s: axi_dma register space not found\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
/* RX channel offset is 0x30 */
|
|
priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
|
|
|
|
priv->phyaddr = -1;
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
|
|
if (offset > 0) {
|
|
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
|
|
priv->phy_of_handle = offset;
|
|
}
|
|
|
|
phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
|
|
if (phy_mode)
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
if (pdata->phy_interface == -1) {
|
|
printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
priv->interface = pdata->phy_interface;
|
|
|
|
priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
|
|
"xlnx,eth-hasnobuf");
|
|
|
|
printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
|
|
priv->phyaddr, phy_string_for_interface(priv->interface));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id axi_emac_ids[] = {
|
|
{ .compatible = "xlnx,axi-ethernet-1.00.a" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(axi_emac) = {
|
|
.name = "axi_emac",
|
|
.id = UCLASS_ETH,
|
|
.of_match = axi_emac_ids,
|
|
.ofdata_to_platdata = axi_emac_ofdata_to_platdata,
|
|
.probe = axi_emac_probe,
|
|
.remove = axi_emac_remove,
|
|
.ops = &axi_emac_ops,
|
|
.priv_auto_alloc_size = sizeof(struct axidma_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|