mirror of
https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
145 lines
2.9 KiB
C
145 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <wdt.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CORE0_WDOG_OFFSET 0x40000
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#define CORE0_POKE_OFFSET 0x50000
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#define CORE0_POKE_OFFSET_MASK 0xfffffULL
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#define WDOG_MODE GENMASK_ULL(1, 0)
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#define WDOG_LEN GENMASK_ULL(19, 4)
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#define WDOG_CNT GENMASK_ULL(43, 20)
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struct octeontx_wdt {
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void __iomem *reg;
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struct clk clk;
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};
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static int octeontx_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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struct octeontx_wdt *priv = dev_get_priv(dev);
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u64 clk_rate, val;
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u64 tout_wdog;
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clk_rate = clk_get_rate(&priv->clk);
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if (IS_ERR_VALUE(clk_rate))
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return -EINVAL;
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/* Watchdog counts in 1024 cycle steps */
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tout_wdog = (clk_rate * timeout_ms / 1000) >> 10;
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/*
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* We can only specify the upper 16 bits of a 24 bit value.
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* Round up
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*/
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tout_wdog = (tout_wdog + 0xff) >> 8;
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/* If the timeout overflows the hardware limit, set max */
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if (tout_wdog >= 0x10000)
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tout_wdog = 0xffff;
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val = FIELD_PREP(WDOG_MODE, 0x3) |
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FIELD_PREP(WDOG_LEN, tout_wdog) |
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FIELD_PREP(WDOG_CNT, tout_wdog << 8);
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writeq(val, priv->reg + CORE0_WDOG_OFFSET);
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return 0;
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}
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static int octeontx_wdt_stop(struct udevice *dev)
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{
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struct octeontx_wdt *priv = dev_get_priv(dev);
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writeq(0, priv->reg + CORE0_WDOG_OFFSET);
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return 0;
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}
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static int octeontx_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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octeontx_wdt_stop(dev);
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/* Start with 100ms timeout to expire immediately */
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octeontx_wdt_start(dev, 100, flags);
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return 0;
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}
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static int octeontx_wdt_reset(struct udevice *dev)
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{
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struct octeontx_wdt *priv = dev_get_priv(dev);
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writeq(~0ULL, priv->reg + CORE0_POKE_OFFSET);
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return 0;
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}
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static int octeontx_wdt_remove(struct udevice *dev)
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{
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octeontx_wdt_stop(dev);
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return 0;
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}
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static int octeontx_wdt_probe(struct udevice *dev)
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{
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struct octeontx_wdt *priv = dev_get_priv(dev);
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int ret;
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priv->reg = dev_remap_addr(dev);
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if (!priv->reg)
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return -EINVAL;
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/*
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* Save base register address in reg masking lower 20 bits
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* as 0xa0000 appears when extracted from the DT
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*/
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priv->reg = (void __iomem *)(((u64)priv->reg &
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~CORE0_POKE_OFFSET_MASK));
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret)
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return ret;
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return 0;
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}
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static const struct wdt_ops octeontx_wdt_ops = {
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.reset = octeontx_wdt_reset,
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.start = octeontx_wdt_start,
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.stop = octeontx_wdt_stop,
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.expire_now = octeontx_wdt_expire_now,
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};
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static const struct udevice_id octeontx_wdt_ids[] = {
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{ .compatible = "arm,sbsa-gwdt" },
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{}
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};
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U_BOOT_DRIVER(wdt_octeontx) = {
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.name = "wdt_octeontx",
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.id = UCLASS_WDT,
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.of_match = octeontx_wdt_ids,
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.ops = &octeontx_wdt_ops,
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.priv_auto = sizeof(struct octeontx_wdt),
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.probe = octeontx_wdt_probe,
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.remove = octeontx_wdt_remove,
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.flags = DM_FLAG_OS_PREPARE,
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};
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