mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 04:36:16 +09:00
49508d4c59
The Blackfin on-chip BootROM requires that fill operations (which is used for the bss) be aligned to 4 bytes (base addr and total len). Plus, the Blackfin early init asm code assumes the same thing. So rather than making things work for no real gain, make sure the bss len is padded to 4 bytes in the linker script. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
155 lines
3.4 KiB
ArmAsm
155 lines
3.4 KiB
ArmAsm
/*
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* U-boot - u-boot.lds.S
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*
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* Copyright (c) 2005-2010 Analog Device Inc.
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/blackfin.h>
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#undef ALIGN
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#undef ENTRY
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#ifndef LDS_BOARD_TEXT
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# define LDS_BOARD_TEXT
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#endif
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/* If we don't actually load anything into L1 data, this will avoid
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* a syntax error. If we do actually load something into L1 data,
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* we'll get a linker memory load error (which is what we'd want).
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* This is here in the first place so we can quickly test building
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* for different CPU's which may lack non-cache L1 data.
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*/
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#ifndef L1_DATA_B_SRAM
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# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
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# define L1_DATA_B_SRAM_SIZE 0
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#endif
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/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
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#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
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# define L1_CODE_ORIGIN L1_INST_SRAM
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#else
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# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
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#endif
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OUTPUT_ARCH(bfin)
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MEMORY
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{
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#if CONFIG_MEM_SIZE
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ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
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# define ram_code ram
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# define ram_data ram
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#else
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# define ram_code l1_code
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# define ram_data l1_data
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#endif
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l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
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l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
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}
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ENTRY(_start)
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SECTIONS
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{
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.text.pre :
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{
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arch/blackfin/cpu/start.o (.text .text.*)
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LDS_BOARD_TEXT
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} >ram_code
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.text.init :
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{
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arch/blackfin/cpu/initcode.o (.text .text.*)
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} >ram_code
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__initcode_lma = LOADADDR(.text.init);
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__initcode_len = SIZEOF(.text.init);
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.text :
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{
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*(.text .text.*)
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} >ram_code
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.rodata :
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{
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. = ALIGN(4);
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*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
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. = ALIGN(4);
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} >ram_data
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.data :
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{
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. = ALIGN(4);
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*(.data .data.*)
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*(.data1)
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*(.sdata)
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*(.sdata2)
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*(.dynamic)
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CONSTRUCTORS
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} >ram_data
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.u_boot_cmd :
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{
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___u_boot_cmd_start = .;
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*(.u_boot_cmd)
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___u_boot_cmd_end = .;
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} >ram_data
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.text_l1 :
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{
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. = ALIGN(4);
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__stext_l1 = .;
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*(.l1.text)
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. = ALIGN(4);
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__etext_l1 = .;
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} >l1_code AT>ram_code
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__text_l1_lma = LOADADDR(.text_l1);
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__text_l1_len = SIZEOF(.text_l1);
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ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
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.data_l1 :
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{
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. = ALIGN(4);
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__sdata_l1 = .;
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*(.l1.data)
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*(.l1.bss)
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. = ALIGN(4);
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__edata_l1 = .;
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} >l1_data AT>ram_data
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__data_l1_lma = LOADADDR(.data_l1);
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__data_l1_len = SIZEOF(.data_l1);
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ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!")
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.bss :
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{
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. = ALIGN(4);
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*(.sbss) *(.scommon)
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*(.dynbss)
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*(.bss .bss.*)
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*(COMMON)
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. = ALIGN(4);
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} >ram_data
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__bss_vma = ADDR(.bss);
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__bss_len = SIZEOF(.bss);
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}
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