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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Guennadi Liakhovetski](/assets/img/avatar_default.png)
SMDK6400 can only boot U-Boot from NAND-flash. This patch adds a nand_spl driver for it too. The board can also boot from the NOR flash, but due to hardware limitations it can only address 64KiB on it, which is not enough for U-Boot. Based on the original sources by Samsung for U-Boot 1.1.6. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
317 lines
6.7 KiB
ArmAsm
317 lines
6.7 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the Samsung SMDK2410 by
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* (C) Copyright 2008
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* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <s3c6400.h>
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#ifdef CONFIG_SERIAL1
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#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET)
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#elif defined(CONFIG_SERIAL2)
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#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET)
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#else
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#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET)
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#endif
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_TEXT_BASE:
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.word TEXT_BASE
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.globl lowlevel_init
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lowlevel_init:
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mov r12, lr
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/* LED on only #8 */
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ldr r0, =ELFIN_GPIO_BASE
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ldr r1, =0x55540000
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str r1, [r0, #GPNCON_OFFSET]
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ldr r1, =0x55555555
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str r1, [r0, #GPNPUD_OFFSET]
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ldr r1, =0xf000
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str r1, [r0, #GPNDAT_OFFSET]
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/* Disable Watchdog */
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ldr r0, =0x7e000000 @0x7e004000
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orr r0, r0, #0x4000
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mov r1, #0
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str r1, [r0]
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/* External interrupt pending clear */
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ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/
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ldr r1, [r0]
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str r1, [r0]
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ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000
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ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000
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/* Disable all interrupts (VIC0 and VIC1) */
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mvn r3, #0x0
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str r3, [r0, #oINTMSK]
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str r3, [r1, #oINTMSK]
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/* Set all interrupts as IRQ */
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mov r3, #0x0
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str r3, [r0, #oINTMOD]
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str r3, [r1, #oINTMOD]
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/* Pending Interrupt Clear */
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mov r3, #0x0
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str r3, [r0, #oVECTADDR]
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str r3, [r1, #oVECTADDR]
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/* init system clock */
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bl system_clock_init
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#ifndef CONFIG_NAND_SPL
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/* for UART */
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bl uart_asm_init
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#endif
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#ifdef CONFIG_BOOT_NAND
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/* simple init for NAND */
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bl nand_asm_init
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#endif
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bl mem_ctrl_asm_init
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/* Wakeup support. Don't know if it's going to be used, untested. */
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ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET)
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ldr r1, [r0]
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bic r1, r1, #0xfffffff7
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cmp r1, #0x8
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beq wakeup_reset
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1:
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mov lr, r12
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mov pc, lr
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wakeup_reset:
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/* Clear wakeup status register */
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ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET)
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ldr r1, [r0]
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str r1, [r0]
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/* LED test */
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ldr r0, =ELFIN_GPIO_BASE
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ldr r1, =0x3000
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str r1, [r0, #GPNDAT_OFFSET]
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/* Load return address and jump to kernel */
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ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET)
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/* r1 = physical address of s3c6400_cpu_resume function */
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ldr r1, [r0]
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/* Jump to kernel (sleep-s3c6400.S) */
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mov pc, r1
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nop
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nop
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/*
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* system_clock_init: Initialize core clock and bus clock.
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* void system_clock_init(void)
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*/
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system_clock_init:
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ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */
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#ifdef CONFIG_SYNC_MODE
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ldr r1, [r0, #OTHERS_OFFSET]
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mov r2, #0x40
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orr r1, r1, r2
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str r1, [r0, #OTHERS_OFFSET]
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nop
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nop
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nop
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nop
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nop
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ldr r2, =0x80
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orr r1, r1, r2
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str r1, [r0, #OTHERS_OFFSET]
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check_syncack:
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ldr r1, [r0, #OTHERS_OFFSET]
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ldr r2, =0xf00
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and r1, r1, r2
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cmp r1, #0xf00
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bne check_syncack
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#else /* ASYNC Mode */
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nop
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nop
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nop
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nop
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nop
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/*
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* This was unconditional in original Samsung sources, but it doesn't
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* seem to make much sense on S3C6400.
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*/
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#ifndef CONFIG_S3C6400
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ldr r1, [r0, #OTHERS_OFFSET]
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bic r1, r1, #0xC0
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orr r1, r1, #0x40
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str r1, [r0, #OTHERS_OFFSET]
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wait_for_async:
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ldr r1, [r0, #OTHERS_OFFSET]
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and r1, r1, #0xf00
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cmp r1, #0x0
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bne wait_for_async
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#endif
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ldr r1, [r0, #OTHERS_OFFSET]
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bic r1, r1, #0x40
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str r1, [r0, #OTHERS_OFFSET]
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#endif
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mov r1, #0xff00
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orr r1, r1, #0xff
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str r1, [r0, #APLL_LOCK_OFFSET]
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str r1, [r0, #MPLL_LOCK_OFFSET]
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/* Set Clock Divider */
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ldr r1, [r0, #CLK_DIV0_OFFSET]
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bic r1, r1, #0x30000
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bic r1, r1, #0xff00
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bic r1, r1, #0xff
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ldr r2, =CLK_DIV_VAL
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orr r1, r1, r2
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str r1, [r0, #CLK_DIV0_OFFSET]
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ldr r1, =APLL_VAL
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str r1, [r0, #APLL_CON_OFFSET]
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ldr r1, =MPLL_VAL
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str r1, [r0, #MPLL_CON_OFFSET]
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/* FOUT of EPLL is 96MHz */
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ldr r1, =0x200203
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str r1, [r0, #EPLL_CON0_OFFSET]
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ldr r1, =0x0
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str r1, [r0, #EPLL_CON1_OFFSET]
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/* APLL, MPLL, EPLL select to Fout */
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ldr r1, [r0, #CLK_SRC_OFFSET]
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orr r1, r1, #0x7
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str r1, [r0, #CLK_SRC_OFFSET]
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/* wait at least 200us to stablize all clock */
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mov r1, #0x10000
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1: subs r1, r1, #1
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bne 1b
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/* Synchronization for VIC port */
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#if defined(CONFIG_SYNC_MODE)
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ldr r1, [r0, #OTHERS_OFFSET]
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orr r1, r1, #0x20
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str r1, [r0, #OTHERS_OFFSET]
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#elif !defined(CONFIG_S3C6400)
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/* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */
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ldr r1, [r0, #OTHERS_OFFSET]
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bic r1, r1, #0x20
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str r1, [r0, #OTHERS_OFFSET]
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#endif
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mov pc, lr
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#ifndef CONFIG_NAND_SPL
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/*
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* uart_asm_init: Initialize UART's pins
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*/
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uart_asm_init:
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/* set GPIO to enable UART */
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ldr r0, =ELFIN_GPIO_BASE
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ldr r1, =0x220022
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str r1, [r0, #GPACON_OFFSET]
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mov pc, lr
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#endif
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#ifdef CONFIG_BOOT_NAND
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/*
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* NAND Interface init for SMDK6400
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*/
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nand_asm_init:
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ldr r0, =ELFIN_NAND_BASE
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ldr r1, [r0, #NFCONF_OFFSET]
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orr r1, r1, #0x70
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orr r1, r1, #0x7700
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str r1, [r0, #NFCONF_OFFSET]
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ldr r1, [r0, #NFCONT_OFFSET]
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orr r1, r1, #0x07
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str r1, [r0, #NFCONT_OFFSET]
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mov pc, lr
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#endif
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#ifdef CONFIG_ENABLE_MMU
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/*
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* MMU Table for SMDK6400
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*/
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/* form a first-level section entry */
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.macro FL_SECTION_ENTRY base,ap,d,c,b
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.word (\base << 20) | (\ap << 10) | \
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(\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1)
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.endm
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.section .mmudata, "a"
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.align 14
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/* the following alignment creates the mmu table at address 0x4000. */
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.globl mmu_table
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mmu_table:
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.set __base, 0
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/* 1:1 mapping for debugging */
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.rept 0xA00
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FL_SECTION_ENTRY __base, 3, 0, 0, 0
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.set __base, __base + 1
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.endr
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/* access is not allowed. */
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.rept 0xC00 - 0xA00
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.word 0x00000000
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.endr
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/* 128MB for SDRAM 0xC0000000 -> 0x50000000 */
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.set __base, 0x500
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.rept 0xC80 - 0xC00
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FL_SECTION_ENTRY __base, 3, 0, 1, 1
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.set __base, __base + 1
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.endr
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/* access is not allowed. */
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.rept 0x1000 - 0xc80
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.word 0x00000000
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.endr
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#endif
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