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https://github.com/brain-hackers/u-boot-brain
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422cb08acb
The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
61 lines
1.3 KiB
C
61 lines
1.3 KiB
C
/*
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* Copyright (C) 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_MC_H__
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#define __FSL_MC_H__
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#include <common.h>
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#define MC_CCSR_BASE_ADDR \
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((struct mc_ccsr_registers __iomem *)0x8340000)
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#define BIT(x) (1 << (x))
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#define GCR1_P1_STOP BIT(31)
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#define GCR1_P2_STOP BIT(30)
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#define GCR1_P1_DE_RST BIT(23)
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#define GCR1_P2_DE_RST BIT(22)
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#define GCR1_M1_DE_RST BIT(15)
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#define GCR1_M2_DE_RST BIT(14)
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#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST)
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#define GSR_FS_MASK 0x3fffffff
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#define MCFAPR_PL_MASK (0x1 << 18)
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#define MCFAPR_BMT_MASK (0x1 << 17)
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#define MCFAPR_BYPASS_ICID_MASK \
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(MCFAPR_PL_MASK | MCFAPR_BMT_MASK)
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#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000)
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#define SOC_MC_PORTAL_STRIDE 0x10000
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#define SOC_MC_PORTAL_ADDR(_portal_id) \
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((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \
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(_portal_id) * SOC_MC_PORTAL_STRIDE))
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struct mc_ccsr_registers {
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u32 reg_gcr1;
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u32 reserved1;
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u32 reg_gsr;
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u32 reserved2;
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u32 reg_sicbalr;
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u32 reg_sicbahr;
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u32 reg_sicapr;
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u32 reserved3;
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u32 reg_mcfbalr;
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u32 reg_mcfbahr;
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u32 reg_mcfapr;
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u32 reserved4[0x2f1];
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u32 reg_psr;
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u32 reserved5;
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u32 reg_brr[2];
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u32 reserved6[0x80];
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u32 reg_error[];
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};
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int mc_init(bd_t *bis);
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int get_mc_boot_status(void);
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unsigned long mc_get_dram_block_size(void);
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#endif
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